CoolRunner-II器件使用施密特触发器
发布时间:2008/9/17 0:00:00 访问次数:683
coolrunner-ii器件中的每个输入/输出脚都具有施密特触发器(schmitt trigger)的功能,并可提供500 mv的磁滞范围。该功能除了能够有效地抑制噪声和用于模拟信号的接收之外,还可用于rc振荡回路,为系统提供灵活和廉价的时钟信号。该功能可以通过属性控制来使能和旁路。
(1)约束文件(ucf)
net (signal name) schmitt_trigger;
例如:
net data_in schmitt_trigger;
net clock schmitt_trigger;
(2)vhdl语言
attribute schi4itt_trigger : string;
attribute schmitt_trigger of <signal name>: signal is "true";
例如:
attribute schmitt_trigger : string;
attribute schmitt_trigger of data_in : signal is "true";
attribute schmitt_trigger of clock : signal is "true";
(3)verilog语言
//synthesis attribute schmitt_trigger of <signal name>;
例如:
//synthesis attribute schmitt_trigger of data_in;
//synthesis attribute schmitt_trigger of clock;
欢迎转载,信息来自维库电子市场网(www.dzsc.com)
(1)约束文件(ucf)
net (signal name) schmitt_trigger;
例如:
net data_in schmitt_trigger;
net clock schmitt_trigger;
(2)vhdl语言
attribute schi4itt_trigger : string;
attribute schmitt_trigger of <signal name>: signal is "true";
例如:
attribute schmitt_trigger : string;
attribute schmitt_trigger of data_in : signal is "true";
attribute schmitt_trigger of clock : signal is "true";
(3)verilog语言
//synthesis attribute schmitt_trigger of <signal name>;
例如:
//synthesis attribute schmitt_trigger of data_in;
//synthesis attribute schmitt_trigger of clock;
欢迎转载,信息来自维库电子市场网(www.dzsc.com)
coolrunner-ii器件中的每个输入/输出脚都具有施密特触发器(schmitt trigger)的功能,并可提供500 mv的磁滞范围。该功能除了能够有效地抑制噪声和用于模拟信号的接收之外,还可用于rc振荡回路,为系统提供灵活和廉价的时钟信号。该功能可以通过属性控制来使能和旁路。
(1)约束文件(ucf)
net (signal name) schmitt_trigger;
例如:
net data_in schmitt_trigger;
net clock schmitt_trigger;
(2)vhdl语言
attribute schi4itt_trigger : string;
attribute schmitt_trigger of <signal name>: signal is "true";
例如:
attribute schmitt_trigger : string;
attribute schmitt_trigger of data_in : signal is "true";
attribute schmitt_trigger of clock : signal is "true";
(3)verilog语言
//synthesis attribute schmitt_trigger of <signal name>;
例如:
//synthesis attribute schmitt_trigger of data_in;
//synthesis attribute schmitt_trigger of clock;
欢迎转载,信息来自维库电子市场网(www.dzsc.com)
(1)约束文件(ucf)
net (signal name) schmitt_trigger;
例如:
net data_in schmitt_trigger;
net clock schmitt_trigger;
(2)vhdl语言
attribute schi4itt_trigger : string;
attribute schmitt_trigger of <signal name>: signal is "true";
例如:
attribute schmitt_trigger : string;
attribute schmitt_trigger of data_in : signal is "true";
attribute schmitt_trigger of clock : signal is "true";
(3)verilog语言
//synthesis attribute schmitt_trigger of <signal name>;
例如:
//synthesis attribute schmitt_trigger of data_in;
//synthesis attribute schmitt_trigger of clock;
欢迎转载,信息来自维库电子市场网(www.dzsc.com)