CY8CLED04D01 ， CY8CLED04D02
CY8CLED04G01 ， CY8CLED03D01
CY8CLED03D02 ， CY8CLED03G01
CY8CLED02D01 ， CY8CLED01D01
13.4寄存器映射银行表0
名字
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
FN0DR
FN0IE
FN0GS
FN0DM2
ADDR
(0,Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
名字
DPWM0PCF
DPWM0PDH
DPWM0PDL
DPWM0PWH
DPWM0PWL
DPWM0PCH
DPWM0PCL
DPWM0GCFG
DPWM1PCF
DPWM1PDH
DPWM1PDL
DPWM1PWH
DPWM1PWL
DPWM1PCH
DPWM1PCL
DPWM1GCFG
DPWM2PCF
DPWM2PDH
DPWM2PDL
DPWM2PWH
DPWM2PWL
DPWM2PCH
DPWM2PCL
DPWM2GCFG
DPWM3PCF
DPWM3PDH
DPWM3PDL
DPWM3PWH
DPWM3PWL
DPWM3PCH
DPWM3PCL
DPWM3GCFG
AMX_IN
AMUX_CFG
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
PAMUX_S1
PAMUX_S2
PAMUX_S3
PAMUX_S4
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
DPWM0PCFG
DPWM1PCFG
DPWM2PCFG
DPWM3PCFG
DPWMINTFLG
DPWMINTMSK
DPWMSYNC
ADDR
(0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
名字
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ADDR
(0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
名字
VDAC0_CR
VDAC0_DR0
VDAC0_DR1
VDAC1_CR
VDAC1_DR0
VDAC1_DR1
VDAC2_CR
VDAC2_DR0
VDAC2_DR1
VDAC3_CR
VDAC3_DR0
VDAC3_DR1
RW
RW
RW
RW
RW
RW
RW
RW
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
ADDR
(0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
PDMUX_S1
PDMUX_S2
PDMUX_S3
PDMUX_S4
PDMUX_S5
PDMUX_S6
CHBOND_CR
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
DBB10DR0
DBB10DR1
DBB10DR2
DBB10CR0
DBB11DR0
DBB11DR1
DBB11DR2
DBB11CR0
DCB12DR0
DCB12DR1
DCB12DR2
DCB12CR0
DCB13DR0
DCB13DR1
DCB13DR2
DCB13CR0
RW
RW
RW
RW
RW
RW
RW
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
VDAC6_CR
VDAC6_DR0
VDAC6_DR1
VDAC4_CR
VDAC4_DR0
VDAC4_DR1
VDAC5_CR
VDAC5_DR0
VDAC5_DR1
MUL1_X
MUL1_Y
MUL1_DH
MUL1_DL
ACC1_DR1
ACC1_DR0
ACC1_DR3
ACC1_DR2
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RDI1RI
RDI1SYN
RDI1IS
RDI1LT0
RDI1LT1
RDI1RO0
RDI1RO1
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
W
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
CPU_F
RL
DAC_D
CPU_SCR1
CPU_SCR0
RW
#
#
文件编号： 001-46319修订版* G
第27页52
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