XRT83L38
八路T1 / E1 / J1 LH /时钟恢复和抖动衰减器SH收发器
修订版1.0.2
T
ABLE
6: R
ECEIVE
T
发芽
C
ONTROL
.............................................................................................................. 32
F
IGURE
13. S
IMPLIFIED
D
IAGRAM的
I
NTERNAL
R
ECEIVE和
T
RANSMIT
T
发芽
M
ODE
........................... 32
T
ABLE
7: R
ECEIVE
T
ERMINATIONS
............................................................................................................................ 32
F
IGURE
14. S
IMPLIFIED
D
IAGRAM FOR
T1
在
E
XTERNAL
T
发芽
M
ODE
（ RXTSEL = 0 ） ................................ 33
F
IGURE
15. S
IMPLIFIED
D
IAGRAM FOR
E1
IN
E
XTERNAL
T
发芽
M
ODE
（ RXTSEL = 0） ...................................... 34
发射器（C
HANNELS
0 - 7) .............................................................................................. 34
发送终止Mode.....................................................................................................................34
T
ABLE
8: T
RANSMIT
T
发芽
C
ONTROL
............................................................................................................ 34
T
ABLE
9: T
发芽
S
ELECT
C
ONTROL
................................................................................................................ 34
外部传输终端模式......................................................................................................34
T
ABLE
10: T
RANSMIT
T
发芽
C
ONTROL
.......................................................................................................... 35
T
ABLE
11: T
RANSMIT
T
ERMINATIONS
........................................................................................................................ 35
冗余APPLICATIONS............................................................................................... 35
典型的冗余方案............................................... ........................................ 36
F
IGURE
16. S
IMPLIFIED
B
LOCK
D
的作者IAGRAM
T
RANSMIT
S
用于挠度
1： 1 & 1 + 1 R
EDUNDANCY
.......................... 37
F
IGURE
17. S
IMPLIFIED
B
LOCK
D
IAGRAM
- R
ECEIVE
S
用于挠度
1:1
和
1+1 R
EDUNDANCY
.................................. 37
F
IGURE
18. S
IMPLIFIED
B
LOCK
D
IAGRAM
- T
RANSMIT
S
用于挠度
N + 1 R
EDUNDANCY
............................................. 38
F
IGURE
19. S
IMPLIFIED
B
LOCK
D
IAGRAM
- R
ECEIVE
S
用于挠度
N + 1 R
EDUNDANCY
............................................... 39
P
ATTERN
T
RANSMIT和
D
ETECT
F
油膏
................................................................................. 40
T
ABLE
12: P
ATTERN变速器控制
.......................................................................................................... 40
T
RANSMIT
A
LL
O
NES
(TAOS)....................................................................................................... 40
N
ETWORK
L
OOP
C
ODE
D
ETECTION和
T
RANSMISSION
................................................................ 40
T
ABLE
13: L
OOP
-C
ODE
D
ETECTION
C
ONTROL
.......................................................................................................... 40
T
RANSMIT和
D
ETECT
Q
UASI
-R
ANDOM
S
IGNAL
S
环境允许
（ TDQRSS ） ........................................... 41
L
OOP
-B
确认
M
副执行秘书办公室
..................................................................................................................... 42
T
ABLE
14: L
OOP
-
BACK IN CONTROL
H
ARDWARE模式
.............................................................................................. 42
T
ABLE
15: L
OOP
-
BACK IN CONTROL
H
OST模式
....................................................................................................... 42
L
OCAL
A
NALOG
L
OOP
-B
确认
（ ALOOP ） .............................. .......................................... 42
F
IGURE
20. L
OCAL
A
NALOG
L
OOP
-
返回信号流
.............................................................................................. 42
R
EMOTE
L
OOP
-B
确认
(RLOOP).................................................................................................... 43
F
IGURE
21. R
EMOTE
L
OOP
-
回来抖动衰减器模式中选择接收路径
.................................. 43
F
IGURE
22. R
EMOTE
L
OOP
-
回来抖动衰减器模式中选择
T
RANSMIT PATH
............................... 43
D
IGITAL
L
OOP
-B
确认
(DLOOP)..................................................................................................... 44
F
IGURE
23. D
IGITAL
L
OOP
-
回来抖动衰减器模式中选择
T
RANSMIT PATH
................................ 44
D
UAL
L
OOP
-B
确认
........................................................................................................................ 44
F
IGURE
24. S
IGNAL流动的
D
UAL LOOP
-
回模式
............................................................................................... 44
微处理器并行接口............................................... ............... 45
T
ABLE
16: M
ICROPROCESSOR接口信号说明
................................................................................ 45
M
ICROPROCESSOR
R
EGISTER
T
ABLES
.......................................................................................... 46
T
ABLE
17: M
ICROPROCESSOR
R
EGISTER
A
地址H1
.................................................................................................. 46
T
ABLE
18: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
...................................................................................... 46
M
ICROPROCESSOR
R
EGISTER
D
ESCRIPTIONS
............................................................................... 50
T
ABLE
19: M
ICROPROCESSOR
R
EGISTER
#0, B
IT
D
ESCRIPTION
................................................................................ 50
T
ABLE
20: M
ICROPROCESSOR
R
EGISTER
#1, B
IT
D
ESCRIPTION
................................................................................ 51
T
ABLE
21: M
ICROPROCESSOR
R
EGISTER
#2, B
IT
D
ESCRIPTION
................................................................................ 53
T
ABLE
22: M
ICROPROCESSOR
R
EGISTER
#3, B
IT
D
ESCRIPTION
................................................................................ 55
T
ABLE
23: M
ICROPROCESSOR
R
EGISTER
#4, B
IT
D
ESCRIPTION
................................................................................ 56
T
ABLE
24: M
ICROPROCESSOR
R
EGISTER
#5, B
IT
D
ESCRIPTION
................................................................................ 58
T
ABLE
25: M
ICROPROCESSOR
R
EGISTER
#6, B
IT
D
ESCRIPTION
................................................................................ 60
T
ABLE
26: M
ICROPROCESSOR
R
EGISTER
#7, B
IT
D
ESCRIPTION
................................................................................ 61
T
ABLE
27: M
ICROPROCESSOR
R
EGISTER
#8, B
IT
D
ESCRIPTION
................................................................................ 62
T
ABLE
28: M
ICROPROCESSOR
R
EGISTER
#9, B
IT
D
ESCRIPTION
................................................................................ 62
T
ABLE
29: M
ICROPROCESSOR
R
EGISTER
#10, B
IT
D
ESCRIPTION
.............................................................................. 63
T
ABLE
30: M
ICROPROCESSOR
R
EGISTER
#11, B
IT
D
ESCRIPTION
.............................................................................. 63
T
ABLE
31: M
ICROPROCESSOR
R
EGISTER
#12, B
IT
D
ESCRIPTION
.............................................................................. 64
T
ABLE
32: M
ICROPROCESSOR
R
EGISTER
#13, B
IT
D
ESCRIPTION
.............................................................................. 64
T
ABLE
33: M
ICROPROCESSOR
R
EGISTER
#14, B
IT
D
ESCRIPTION
.............................................................................. 65
II
