飞思卡尔半导体公司

用户指南

DSP56374UG

0.6修订版， 2004年11月

DSP56374 24位数字信号

处理器的用户指南

本文件包含的新产品信息。

规格书中信息如有变更，恕不另行通知。

飞思卡尔半导体公司2004版权所有。

目录

段

数

页面

数

前言我

第1章

DSP56374概述

1.1

1.2

1.3

1.4

1.4.1

1.4.1.1

1.4.1.2

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

1.4.8

1.4.9

1.5

1.5.1

1.5.2

1.5.3

1.5.4

1.5.5

1.5.6

介绍...............................................................................................................................................................1-1

DSP56300内核描述.....................................................................................................................................1-2

DSP56374音频处理器架构.................................................................................................................1-3

DSP56300核心功能模块...........................................................................................................................1-3

数据ALU ............................................................................................................................................................1-3

数据寄存器ALU ......................................................................................................................................1-3

乘法器 - 累加器（ MAC）的...................................................................................................................1-3

地址产生单元（ AGU ） ........................................................................................................................1-4

节目控制单元（PCU ） ..............................................................................................................................1-4

内部总线......................................................................................................................................................1-4

直接存储器访问（DMA ） ...........................................................................................................................1-5

基于PLL的时钟振荡器................................................................................................................................1-5

片上存储器................................................................................................................................................1-5

片外存储器扩展.............................................................................................................................1-5

电源要求...........................................................................................................................................1-5

外围概述..................................................................................................................................................1-6

通用输入/输出（ GPIO ） ...............................................................................................................1-6

三重计时器（ TEC ） .............................................................................................................................................1-6

增强型串行音频接口（ ESAI ） ............................................................................................................1-7

增强型串行音频接口1 （ ESAI_1 ） .....................................................................................................1-7

串行主机接口（ SHI） .................................................................................................................................1-7

看门狗定时器（ WDT ） ......................................................................................................................................1-7

第2章

SIGNAL /连接描述

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

信号的分组.......................................................................................................................................................2-1

动力.........................................................................................................................................................................2-1

地.......................................................................................................................................................................2-3

SCAN ........................................................................................................................................................................2-4

时钟和PLL ...........................................................................................................................................................2-4

中断和模式控制.......................................................................................................................................2-4

串行主机接口..................................................................................................................................................2-6

增强型串行音频接口...............................................................................................................................2-8

增强型串行音频Interface_1 .........................................................................................................................2-12

专用GPIO - 端口G .........................................................................................................................................2-16

定时器.......................................................................................................................................................................2-18

JTAG /一旦接口.............................................................................................................................................2-19

第3章

内存配置

3.1

3.1.1

3.1.2

3.1.3

数据和程序存储器映射.............................................................................................................................3-1

保留的内存空间...................................................................................................................................3-5

引导代码.................................................................................................................................................3-5

动态内存配置切换......................................................................................................3-5

DSP56374用户指南，版本0.6

初步 - 如有变动

飞思卡尔半导体公司

TOC-1

目录

段

数

3.1.4

3.1.5

3.1.6

3.2

3.3

页面

数

外部存储器支持...................................................................................................................................3-5

DMA和内存..............................................................................................................................................3-5

内存块..............................................................................................................................................3-6

内存补丁模块..............................................................................................................................................3-6

内部I / O存储器映射.........................................................................................................................................3-7

第4章

核心配置

4.1

4.2

4.2.1

4.3

4.4

4.5

4.6

4.6.1

4.6.2

4.6.3

4.6.4

4.6.5

4.6.6

4.7

4.8

介绍...............................................................................................................................................................4-1

经营模式寄存器（ OMR ） ..............................................................................................................................4-1

保留 - 位4 ， 5 ， 10 - 15和23 ..............................................................................................................4-1

操作模式.......................................................................................................................................................4-1

中断优先级寄存器........................................................................................................................................4-3

DMA请求源..............................................................................................................................................4-9

PLL初始化....................................................................................................................................................4-10

PLL预分频因子（ PD0 - PD4 ） .................................................................................................................4-10

PLL倍频因子（ MF0 - MF7 ） ............................................................................................................4-10

PLL反馈倍频（ OD1 ） ......................................................................................................................4-10

PLL输出分频系数（ OD0 ， OD1 ） ............................................................................................................4-10

PLL分频因子（ DF0 - DF2 ） ........................................................................................................................4-10

PLL锁定MUX （ PLKM ） ..............................................................................................................................4-10

设备标识（ ID ）注册.........................................................................................................................4-10

JTAG识别（ ID ）注册..........................................................................................................................4-11

第5章

PLL和时钟发生器

5.1

5.2

5.3

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.4

5.4.1

5.4.2

5.4.3

5.5

5.5.1

5.6

5.7

5.8

5.9

介绍...............................................................................................................................................................5-1

PLL和时钟信号..............................................................................................................................................5-1

PLL模块.................................................................................................................................................................5-1

频预分频器..........................................................................................................................................5-2

鉴相器和电荷泵环路滤波器....................................................................................................5-2

压控振荡器（ VCO ） .................................................................................................................5-2

分频器的PLL ......................................................................................................................................................5-2

PLL倍频因子（ MF ） .........................................................................................................................5-3

PLL操作...........................................................................................................................................................5-3

EXTAL时钟输入处.............................................................................................................................5-3

PLL倍频............................................................................................................................5-3

PLL的输出频率（ PLL输出） ......................................................................................................................5-4

时钟发生器........................................................................................................................................................5-6

低功率分配器（ LPD ） .................................................................................................................................5-6

工作频率（ FOSC ） ......................................................................................................................................5-6

PLL编程模型.........................................................................................................................................5-7

PLL初始化过程...................................................................................................................................5-10

PLL编程实例..................................................................................................................................5-11

第6章

通用输入/输出

6.1

6.2

介绍..............................................................................................................................................................6-1

编程模型..................................................................................................................................................6-1

DSP56374用户指南，版本0.6

初步 - 如有变动

TOC-2

飞思卡尔半导体公司

目录

段

数

6.2.1

6.2.2

6.2.2.1

6.2.2.2

6.2.2.3

6.2.2.4

6.2.3

6.2.3.1

6.2.3.2

6.2.3.3

6.2.4

页面

数

端口C和E信号和寄存器.....................................................................................................................6-1

端口G信号和寄存器...............................................................................................................................6-1

端口G控制寄存器（ PCRG ） ..................................................................................................................6-1

口方向寄存器（ PRRG ） ...............................................................................................................6-1

端口G数据寄存器（ PDRG ） ........................................................................................................................6-2

ESAI / EXTAL时钟控制....................................................................................................................6-2

端口H信号和寄存器...............................................................................................................................6-3

端口H控制寄存器（ PCRH ） ..................................................................................................................6-3

端口H方向寄存器（ PRRH ） ...............................................................................................................6-3

端口H数据寄存器（ PDRH ） ........................................................................................................................6-4

定时/计数器信号..............................................................................................................................6-4

第7章

串行主机接口

7.1

7.2

7.3

7.4

7.4.1

7.4.2

7.4.3

7.4.4

7.4.4.1

7.4.4.2

7.4.5

7.4.5.1

7.4.5.2

7.4.5.3

7.4.5.4

7.4.5.5

7.4.6

7.4.6.1

7.4.6.1.1

7.4.6.2

7.4.6.3

7.4.6.4

7.4.6.5

7.4.6.6

7.4.6.7

7.4.6.8

7.4.6.9

7.4.6.10

7.4.6.11

7.4.6.12

7.4.6.13

7.4.6.14

7.4.6.15

7.4.6.16

7.4.6.17

介绍...............................................................................................................................................................7-1

串行主机接口的内部架构...............................................................................................................7-1

石时钟发生器.................................................................................................................................................7-2

串行主机接口编程模型...............................................................................................................7-2

SHI输入/输出移位寄存器（ IOSR ） -Host侧...................................... .................................................. .7-4

石主机发送数据寄存器（ HTX ） -DSP侧....................................... ................................................. 7 -4

石主机接收数据FIFO （ HRX ） -DSP侧....................................... .................................................. 7-5 .....

施从机地址寄存器（ HSAR ） -DSP侧........................................ .................................................. 7-5 ....

HSAR保留位， 19位，17 0 ..........................................................................................................7-5

HSAR我

2

I2C从地址（ HA [6 ： 3 ] ， HA1 ） -Bits 23-20,18 .............................. ......................................... 7-5

石时钟控制寄存器（ HCKR ） -DSP侧........................................ .................................................. 7-5 ....

时钟相位和极性（ CPHA和CPOL ） -Bits 1-0 .................................... ........................................ 7-5

HCKR预分频器倍率选择（ HRS ）位2 ........................................ .................................................. ....... 7-6

HCKR分频模数选择（ HDM [ 7 ： 0 ] ） - 位10-3 ................................. ........................................... 7-7

HCKR过滤模式（ HFM [ 1 ： 0 ] ） - 位数13-12 .................................. .................................................. ........ 7-7

HCKR保留位， 23-14位， 11 ........................................................................................................7-7

SHI控制/状态寄存器（ HCSR ） -DSP侧....................................... .................................................. 7-7 .....

HCSR主机启用（ HEN ）位0 ...............................................................................................................7-7

SHI个人重置..............................................................................................................................7-8

HCSR我

2

C / SPI选择（ HI2C ）位1 ......................................................................................................7-8

HCSR串行主机接口模式（ HM [ 1 ： 0 ] ） - 位数3-2 ................................ ............................................ 7-8

HCSR我

2

C时钟冻结（ HCKFR ）位4 ..................................................................................................7-8

HCSR FIFO使能控制（ HFIFO ）位5 ....................................... .................................................. 7-8 ....

HCSR主模式（ HMST ）位6 ...........................................................................................................7-8

HCSR主机请求使能（的haltRQ hrqe [ 1 ： 0 ] ） - 位8-7 ................................ ................................................. 7 -9

HCSR空闲（ HIDLE ）位9 .........................................................................................................................7-9

HCSR总线错误中断使能（ HBIE ）位10 ...................................... ............................................... 7-9

HCSR发送中断使能（ HTIE ）位....................................... 11 ............................................... 7-9

HCSR接收中断使能（ HRIE [ 1 ： 0 ] ） - 位数13-12 ................................. ...................................... 7-10

HCSR主机发送溢出错误（ HTUE ）位....................................... 14 ..................................... 7-10

HCSR主机发送数据空（ HTDE ）位....................................... 15 .......................................... 7-10

HCSR保留位， 23位， 18和16 .................................................................................................7-10

主机接收FIFO不为空（ HRNE ）位....................................... 17 ............................................... 7-10

主机接收FIFO满（ HRFF ）位19 ..................................................................................................7-10

主机接收溢出错误（ HROE ）位20 ........................................ .................................................. .7-11

DSP56374用户指南，版本0.6

初步 - 如有变动

飞思卡尔半导体公司

TOC-3