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PI7C8150A
双端口PCI至PCI桥接器
3.8.4.2
3.8.4.3
TARGET断开................................................ ................................................ 40
TARGET中止............................................................................................................ 40
4
地址译码................................................ ....................................... 41
4.1
地址范围................................................................................................................... 41
4.2
I / O地址DECODING........................................................................................................ 41
4.2.1
I / O基址和限制地址寄存器.......................................... ......................
42
4.2.2
ISA MODE...........................................................................................................................
43
4.3
存储器地址译码方式............................................... ............................................ 43
4.3.1
内存映射I / O基址和限制地址寄存器
......................... 44
4.3.2
预取内存基址和限制地址寄存器
................. 45
4.4
VGA SUPPORT........................................................................................................................... 46
4.4.1
VGA MODE.........................................................................................................................
46
4.4.2
VGA SNOOP MODE...........................................................................................................
46
5
5.1
5.2
5.3
5.4
事务排序................................................ ............................ 47
交易治理BY排序规则............................................. .......... 47
一般订购指南............................................... ...................................... 48
订购RULES.................................................................................................................... 48
数据同步................................................ .................................................. .. 51
6
错误处理................................................ ........................................... 52
6.1
地址奇偶校验错误............................................... .................................................. ... 52
6.2
数据奇偶校验错误........................................................................................................... 53
6.2.1
配置写入事务配置空间..........
53
6.2.2
读事务
.................................................................................................... 53
6.2.3
延迟写入交易............................................... ................................
54
6.2.4
张贴写事务............................................... ...................................
57
6.3
数据奇偶校验错误报告摘要............................................. .................... 58
6.4
系统错误（ SERR_L ）报告............................................ ................................... 62
7
独占访问................................................ ........................................ 63
7.1
并发锁............................................................................................................. 63
7.2
获取独占访问ACROSS PI7C8150A ............................................. ....... 63
7.2.1
下行方向锁定交易
..................................... 63
7.2.2
锁定事务对上游方向
.............................................. 65
7.3
ENDING EXCLUSIVE ACCESS................................................................................................ 65
8
PCI总线仲裁............................................... .................................... 66
8.1
主PCI总线仲裁.............................................. .......................................... 66
8.2
二级PCI总线仲裁.............................................. .................................... 66
8.2.1
辅助总线仲裁使用内部仲裁器....................
66
8.2.2
PREEMPTION
.................................................................................................................... 68
8.2.3
辅助总线仲裁使用外部仲裁器......................
68
8.2.4
BUS PARKING....................................................................................................................
68
9
9.1
9.2
CLOCKS................................................................................................................ 69
主时钟INPUTS....................................................................................................... 69
二级时钟输出............................................... ............................................. 69
10
通用I / O接口............................................ .............. 69
第111 6
2006年4月 - 修订版1.1
06-0057
