AX88195本地CPU总线快速以太网MAC控制器
目录
1.0简介.............................................................................................................................................. 4
1.1 G
ENERAL
D
ESCRIPTION
:..................................................................................................................................... 4
1.2 AX88195 B
LOCK
D
IAGRAM
: .............................................................................................................................. 4
1.3 AX88195 P
IN
C
ONNECTION
D
IAGRAM
............................................................................................................... 5
1.3.1 AX88195引脚连接图ISA总线模式....................................... ......................................... 6
1.3.2 AX88195引脚连接图80x86的模式........................................ ........................................... 7
1.3.3 AX88195引脚连接图MC68K模式........................................ ........................................ 8
1.3.4 AX88195引脚连接图MCS- 51模式...................................... ......................................... 9
2.0信号描述................................................................................................................................. 10
2.1 L
OCAL
CPU B
US
I
覆盖整个院落
S
IGNALS
G
ROUP
................................................................................................... 10
2.2 MII
接口信号集团
........................................................................................................................ 11
2.3 EEPROM S
IGNALS
G
ROUP
.............................................................................................................................. 12
2.4 SRAM我
覆盖整个院落销集团
......................................................................................................................... 12
2.5 M
ISCELLANEOUS销集团
............................................................................................................................ 12
2.6 P
OWER的配置设置信号的交叉引用表
................................................................ 13
3.0内存和I / O MAPPING...................................................................................................................... 14
3.1 EEPROM M
埃默里
M
APPING
.......................................................................................................................... 14
3.2 I / O M
APPING
................................................................................................................................................... 14
3.3 SRAM M
埃默里
M
APPING
.............................................................................................................................. 14
4.0寄存器操作............................................................................................................................. 15
4.1 C
OMMAND
R
EGISTER
（ CR ）O
FFSET
00H （R
EAD
/W
RITE
)................................................................................... 17
4.2 I
NTERRUPT
S
TATUS
R
EGISTER
（ ISR ）O
FFSET
07H （R
EAD
/W
RITE
) ..................................................................... 17
4.3 I
NTERRUPT屏蔽寄存器
（ IMR ）O
FFSET
0FH （W
RITE
) ................................................................................. 18
4.4 D
ATA
C
ONFIGURATION
R
EGISTER
（ DCR ）O
FFSET
0EH （W
RITE
)....................................................................... 18
4.5 T
RANSMIT
C
ONFIGURATION
R
EGISTER
（ TCR ）O
FFSET
0DH （W
RITE
)................................................................ 18
4.6 T
RANSMIT
S
TATUS
R
EGISTER
（ TSR ）O
FFSET
04H （R
EAD
) ................................................................................ 19
4.7 R
ECEIVE
C
ONFIGURATION
（ RCR ）O
FFSET
0CH （W
RITE
) .................................................................................. 19
4.8 R
ECEIVE
S
TATUS
R
EGISTER
（ RSR ）O
FFSET
0CH （R
EAD
) .................................................................................. 19
4.9 I
NTER
-
FRAME GAP
（ IFG ）O
FFSET
16H （R
EAD
/W
RITE
) ...................................................................................... 20
4.10 I
NTER
-
FRAME GAP
S
EGMENT
1 （ IFGS1 ）O
FFSET
12H （R
EAD
/W
RITE
) ............................................................... 20
4.11 I
NTER
-
FRAME GAP
S
EGMENT
2 （ IFGS2 ）O
FFSET
13H （R
EAD
/W
RITE
) ............................................................... 20
4.12 MII / EEPROM M
ANAGEMENT
R
EGISTER
（ MEMR ）O
FFSET
14H （R
EAD
/W
RITE
) .............................................. 20
4.13 T
美东时间
R
EGISTER
（ TR ）O
FFSET
15H （W
RITE
) ................................................................................................... 20
5.0 CPU的I / O读写功能......................................... .................................................. ....... 21
5.1 ISA
总线类型访问功能
. ................................................................................................................... 21
5.2 80186 CPU
总线类型访问功能
......................................................................................................... 21
5.3 MC68K CPU
总线类型访问功能
...................................................................................................... 22
5.3 MCS- 51的CPU
总线类型访问功能
. .................................................................................................... 22
6.0电气性能和时序............................................. ........................................... 23
6.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
........................................................................................................................ 23
6.2 G
ENERAL
O
PERATION
C
ONDITIONS
................................................................................................................... 23
6.3 DC
极特
..................................................................................................................................... 23
6.4交流牛逼
即时通信
C
极特
....................................................................................................................... 24
6.4.1 XTAL / CLOCK........................................................................................................................................ 24
6.4.2复位时序............................................................................................................................................ 24
6.4.3 ISA总线访问Timing............................................................................................................................. 25
6.4.4 80186型I / O访问时序................................................................................................................. 26
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