XRT71D00

修订版1.01

E3 / DS3 / STS -1的抖动衰减器， STS - 1到DS3的失同步

初步



1

1

1

2

概述................................................ ................................................. 1

F

EATURES

....................................................................................................................................................

A

PPLICATIONS

..............................................................................................................................................

B

LOCK

D

的作者IAGRAM

XRT71D00 ............................................................................................................

P

IN

O

的的UT

XRT71D00 （ 32升

EAD

TFQP P

ACKAGE

) ..............................................................................

订购信息................................................ ...............................................

引脚说明..........................................................................................................

电气特性................................................ ..................................

系统说明................................................ .................................................. ..

2

3

6

8

图1.在XRT71D00 （配置在“硬件”模式来操作）的..................... 8

图2.插图的XRT71D00的（配置的“主机”模式进行操作） ................................ 9

B

ACKGROUND

I

载文信息

: ........................................................................................................................ 9

图3.第1类DS3抖动传递面膜......................................... ................................................. 10

抖动衰减： .......................................................................................................................... 10

图4. XRT71D00去同步器的框图........................................... ..................................... 11

T

ABLE

1: F

双模引脚受膏

“H

ARDWARE

” M

ODE配置

......................................... 11

T

ABLE

2: A

地址H1和

B

IT

F

的作者ORMATS

C

OMMAND

R

EGISTERS

............................................................. 12

图5.微处理器串行接口数据结构.......................................... ............................... 13

图6.时序图的微处理器串行接口........................................ .................. 13

图7.输入/输出时序......................................................................................................................14

T

ABLE

3 ： XRT71D00

伊特尔

T

转让（BOT）

F

油膏

......................................................................................... 14

T

ABLE

4 ： XRT71D00 M

AXIMUM

J

伊特尔

T

OLERANCE

........................................................................................ 15

封装信息................................................ .............................................. 16

32引脚TQFP封装尺寸............................................. .......................................... 16

订购信息............................................................................................................. 16

修订记录....................................................................................................................... 17

III