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引脚
120
WLC
SP
D5
D4
D3
C1
C2
引脚名称
默认
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
PTB22
PTB23
PTC0
PTC1/
LLWU_P6
PTC2
ADC0_SE14/
TSI0_CH13
ADC0_SE15/
TSI0_CH14
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
CMP1_IN1
VDD
ADC0_SE14/
TSI0_CH13
ADC0_SE15/
TSI0_CH14
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
CMP1_IN1
VDD
PTB22
PTB23
PTC0
PTC1/
LLWU_P6
PTC2
SPI2_SOUT
SPI2_SIN
SPI0_PCS4
SPI0_PCS3
SPI0_PCS2
SPI0_PCS5
PDB0_EXTRG
I2S0_TXD
FB_AD29
FB_AD28
FB_AD14
FB_AD13
FB_AD12
CMP2_OUT
UART1_RTS_b FTM0_CH0
UART1_CTS_b FTM0_CH1
B1
G7
A3
B4
C5
B5
A4
C6
D6
A5
D7
B6
C7
A6
C4
A7
PTC3/
LLWU_P7
VDD
PTC4/
LLWU_P8
PTC5/
LLWU_P9
PTC6/
LLWU_P10
PTC7
PTC8
PTC9
PTC10
PTC11/
LLWU_P11
PTC12
PTC13
PTC14
PTC15
VDD
PTC16
PTC3/
LLWU_P7
PTC4/
LLWU_P8
PTC5/
LLWU_P9
SPI0_PCS1
UART1_RX
FTM0_CH2
FB_CLKOUT
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART1_TX
FTM0_CH3
LPT0_ALT2
FB_AD11
FB_AD10
FB_AD9
FB_AD8
CMP1_OUT
CMP0_OUT
CMP0_IN0
CMP0_IN1
ADC1_SE4b/
CMP0_IN2
ADC1_SE5b/
CMP0_IN3
ADC1_SE6b/
CMP0_IN4
ADC1_SE7b
CMP0_IN0
CMP0_IN1
ADC1_SE4b/
CMP0_IN2
ADC1_SE5b/
CMP0_IN3
ADC1_SE6b/
CMP0_IN4
ADC1_SE7b
PTC6/
LLWU_P10
PTC7
PTC8
PTC9
PTC10
PTC11/
LLWU_P11
PTC12
PTC13
PTC14
PTC15
PDB0_EXTRG
I2S0_MCLK
I2S0_CLKIN
FB_AD7
FTM2_FLT0
I2S0_RX_BCLK FB_AD6
I2C1_SCL
I2C1_SDA
UART4_RTS_b
UART4_CTS_b
UART4_RX
UART4_TX
CAN1_RX
UART3_RX
I2S0_RX_FS
I2S0_RXD
FB_AD5
FB_RW_b
FB_AD27
FB_AD26
FB_AD25
FB_AD24
FB_CS5_b/
FB_TSIZ1/
FB_BE23_16_b
FB_CS4_b/
FB_TSIZ0/
FB_BE31_24_b
FB_TBST_b /
FB_CS2_b/
FB_BE15_8_b
FB_CS3_b/
FB_BE7_0_b
FB_ALE /
FB_CS1_b/
FB_TS_b
VDD
VDD
PTC16
B7
PTC17
PTC17
CAN1_TX
UART3_TX
C8
PTC18
PTC18
UART3_RTS_b
D8
B8
PTC19
PTD0/
LLWU_P12
PTC19
PTD0/
LLWU_P12
SPI0_PCS0
UART3_CTS_b
UART2_RTS_b
FB_TA_b
K20数据表数据表，版本6.1 ， 08/2012 。
飞思卡尔半导体公司
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