HT66F0172/HT66F0174
增强的A / D闪存的8位MCU
HT66F0174
00H
01H
0½H
0½H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
1½H
1½H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
½0H
½1H
½½H
½½H
½4H
BANK 0 BANK 1
IAR0
MP0
IAR1
MP1
BP
加
的PCl
TBLP
TBLH
TBHP
状态
SMOD
LVDC
INTEG
INTC0
INTC1
INTC½
MFI0
MFI1
MFI½
PA
PAC
PCPU
PAWU
Un½sed
TMPC
WDTC
TBC
Un½sed
Un½sed
EEA
EED
ADRL
ADRH
ADCR0
ADCR1
ACERL
½5H
½6H
½7H
½8H
½9H
½AH
½BH
½CH
½DH
½EH
½FH
½0H
½1H
½½H
½½H
½4H
½5H
½6H
½7H
½8H
½9H
½AH
½BH
½CH
½DH
½EH
BANK 0 BANK 1
Un½sed
CTRL
LVRC
TM0C0
TM0C1
TM0DL
TM0DH
TM0AL
TM0AH
TM0RPL
TM0RPH
TM1C0
TM1C1
TM1DL
TM1DH
TM1AL
TM1AH
TM1RPL
TM1RPH
Un½sed
00H
01H
0½H
0½H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
1½H
1½H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
½0H
½1H
½½H
½½H
½4H
HT66F0172
BANK 0 BANK 1
IAR0
MP0
IAR1
MP1
BP
加
的PCl
TBLP
TBLH
TBHP
状态
SMOD
LVDC
INTEG
INTC0
INTC1
INTC½
MFI0
MFI1
MFI½
PA
PAC
PCPU
PAWU
Un½sed
TMPC
WDTC
TBC
Un½sed
Un½sed
Un½sed
Un½sed
ADRL
ADRH
ADCR0
ADCR1
ACERL
½5H
½6H
½7H
½8H
½9H
½AH
½BH
½CH
½DH
½EH
½FH
½0H
½1H
½½H
½½H
½4H
½5H
½6H
½7H
½8H
½9H
½AH
½BH
½CH
½DH
½EH
½FH
40H
BANK 0 BANK 1
Un½sed
CTRL
LVRC
TM0C0
TM0C1
TM0DL
TM0DH
TM0AL
TM0AH
TM0RPL
TM0RPH
TM1C0
TM1C1
TM1DL
TM1DH
TM1AL
TM1AH
TM1RPL
TM1RPH
Un½sed
PC
PCC
PCPU
PB
中国人民银行
PBPU
阅读0 ＆ frac12 ;＆ frac12 ;
PC
PCC
PCPU
PB
中国人民银行
PBPU
½FH
40H
阅读0 ＆ frac12 ;＆ frac12 ;
欧洲经济共同体
Un½sed
Un½sed
7FH
7FH
：UN ＆ frac12 ; SED ＆ frac12 ;读为00H
：UN ＆ frac12 ; SED ＆ frac12 ;读为00H
数据存储结构
总体数据存储器分为两个存储体。该专用数据存储器寄存器
accessible in all banks, with the exception of the EEC register at address 40H, which is only accessible
in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer
to the correct value. The start address of the Data Memory for the device is the address 00H.
1.00版
½½
＆ frac12 ;＆ frac12 ;＆ frac12 ;＆ frac12 ; 11 ＆ frac12 ; ＆ frac12 ; 01 ＆ frac12 ;
