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引脚
144 144
LQF地图
P BGA
37
M3
引脚名称
默认
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
VREF_OUT /
CMP1_IN5/
CMP0_IN5/
ADC1_SE1
8
DAC0_OUT/
CMP1_IN3/
ADC0_SE2
3
DAC1_OUT/
CMP2_IN3/
ADC1_SE2
3
XTAL32
EXTAL32
VBAT
VDD
VSS
PTE24
PTE25
PTE26
PTE27
PTE28
PTA0
VREF_OUT /
CMP1_IN5/
CMP0_IN5/
ADC1_SE1
8
DAC0_OUT/
CMP1_IN3/
ADC0_SE2
3
DAC1_OUT/
CMP2_IN3/
ADC1_SE2
3
XTAL32
EXTAL32
VBAT
VDD
VSS
ADC0_SE1
7
ADC0_SE1
8
残
残
残
JTAG_TCL
K/
SWD_CLK /
EZP_CLK
JTAG_TDI /
EZP_DI
VREF_OUT /
CMP1_IN5/
CMP0_IN5/
ADC1_SE1
8
DAC0_OUT/
CMP1_IN3/
ADC0_SE2
3
DAC1_OUT/
CMP2_IN3/
ADC1_SE2
3
XTAL32
EXTAL32
VBAT
VDD
VSS
ADC0_SE1
7
ADC0_SE1
8
PTE24
PTE25
PTE26
PTE27
PTE28
TSI0_CH1
PTA0
UART0_CT
S ← B
FTM0_CH5
JTAG_TCL
K/
SWD_CLK
JTAG_TDI
EZP_CLK
CAN1_TX
CAN1_RX
UART4_TX
UART4_RX
UART4_CT
S ← B
UART4_RT
S ← B
EWM_OUT
_b
EWM_IN
RTC_CLKO
UT
38
L3
39
L4
40
41
42
43
44
45
46
47
48
49
50
M7
M6
L6
—
—
M4
K5
K4
J4
H4
J5
51
52
J6
K6
PTA1
PTA2
TSI0_CH2
PTA1
PTA2
UART0_RX
UART0_TX
FTM0_CH6
FTM0_CH7
EZP_DI
JTAG_TDO / TSI0_CH3
TRACE_SW
O / EZP_DO
JTAG_TMS / TSI0_CH4
SWD_DIO
NMI_b /
EZP_CS_b
残
VDD
VSS
残
ADC0_SE1
0
ADC0_SE1
0
VDD
VSS
TSI0_CH5
JTAG_TDO / EZP_DO
TRACE_SW
O
JTAG_TMS /
SWD_DIO
NMI_B
CMP2_OUT I2S0_RX_B
CLK
JTAG_TRS
T
EZP_CS_b
53
54
55
56
57
58
59
K7
L7
M8
E7
G7
J7
J8
PTA3
PTA4
PTA5
VDD
VSS
PTA6
PTA7
PTA3
PTA4
PTA5
UART0_RT
S ← B
FTM0_CH0
FTM0_CH1
FTM0_CH2
PTA6
PTA7
FTM0_CH3
FTM0_CH4
TRACE_CL
KOUT
TRACE_D3
K10次系列数据手册数据手册,第6 , 9/2011 。
飞思卡尔半导体公司
61