XRT73R12

十二通道E3 / DS3 / STS - 1线路接口单元

2007年10月

修订版1.0.3

概述

该XRT73R12是一个12通道的完全集成

线路接口单元（LIU ），具有Exar的

3

技术（可重构， Relayless冗余）

对于E3 / DS3 / STS - 1的应用程序。刘整合

在12个独立的接收器和发射器

单420铅TBGA封装。

在XRT73R12的每个通道可

独立配置的E3操作（ 34.368

兆赫） ，DS3 （ 44.736兆赫）或STS -1（ 51.84兆赫） 。

每个发射器可以被关闭，并且三态

冗余支持或节省电力。

该XRT73R12的差分接收器提供了高

噪声干扰余量，并且能够接收数据

超过1000英尺的电缆或电缆的高达12分贝

衰减。

F

IGURE

1. B

LOCK

D

的作者IAGRAM

XRT 73R12

该XRT73R12提供了一个并行微处理器

接口进行编程和控制。

该XRT73R12支持模拟，远程和数字

环边后卫。该设备还具有一个内置的伪

随机二进制序列（ PRBS ）发生器和

检测器与插入和检测单个位的能力

错误诊断目的。

应用

E3 / DS3接入设备

DSLAM设备

数字交叉连接系统

CSU / DSU设备

路由器

光纤终端

CS

RD

WR

ADDR [ 7：0]

D[7:0]

PCLK

RDY

INT

PMODE

RESET

XRT73R12

CLKOUT_n

μprocessor

接口

SFM_EN

RLOL_n

E3Clk

DS3Clk

STS-Clk/12M

MUX

峰值检波器

切片机

时钟&数据

恢复

LOS

探测器

时钟

合成

HDB3/

B3ZS

解码器

RxClk_n

RxPOS_n

RxNEG / LCV_n

RTIP_n

RRING_n

AGC /

均衡器

当地

环回

远程

环回

RLOS_n

TxClk_n

TxPOS_n

TxNEG_n

TTIP_n

TRING_n

MTIP_n

MRing_n

DMO_n

信息和通信技术

LINE

司机

Tx

脉冲

成型

定时

控制

MUX

HDB3/

B3ZS

编码器

设备

MONITOR

Tx

控制

TXON

通道0

通道n ...

CHANNEL 11

订购信息

P

艺术

N

棕土

XRT73R12IB

P

ACKAGE

420铅TBGA

O

操作摄像机

T

emperature

R

ANGE

-40

°

C至+ 85

°

C

Exar公司

公司48720加藤道，弗里蒙特CA， 94538

(510) 668-7000

传真（ 510 ） 668-7017

www.exar.com

XRT73R12

十二通道E3 / DS3 / STS - 1线路接口单元

修订版1.0.3

特点

接收器

- 40 ° C至85°C工业级温度范围

发送接口特性

（可重构，

Relayless

R

3

技术

冗余）

输入抖动容限

接受来自任何单轨或双轨数据

终端设备，并产生一个双极性信号

到行

片上时钟和数据恢复电路高

会见E3 / DS3 / STS - 1抖动容限要求

检测并清除LOS按G.775

接收监控模式处理多达20分贝平

与6分贝电缆的衰减损耗

集成的脉冲整形电路

内置B3ZS / HDB3编码器（其可以是

禁用）

接受发送时钟为30％占空比 -

70%

芯片B3ZS / HDB3编码器和解码器，可

可以启用或禁用

生成符合ITU -T G.703脉冲

对于E3应用脉冲模板

片上时钟合成器提供适当的

从单一12.288 MHz的时钟速率时钟

生成符合DSX - 3脉冲的脉冲

模板，如在符合Bellcore GR -499中指定

-core

和ANSI T1.102_1993

提供低抖动输出时钟

发射机

生成符合STSX - 1脉冲

脉冲模板，如在Bellcore的指定GR- 253-

CORE

Relayless

R

3

技术

冗余）

（可重构，

发射机可以以支持被关闭

冗余设计

接收接口特性

符合符合Bellcore GR - 499 ， GR- 253和ANSI

T1.102规范发射脉冲

三态的冗余发送输出能力

应用

集成自适应接收均衡（可选）

最佳的时钟和数据恢复

每个发射器可以被独立地接通

或OFF

声明并清除按照ITU-T的LOS缺陷

为E3和DS3应用G.775的要求

变送器提供电压输出驱动器

控制和诊断

会见抖动容限要求，规定

在ITU -T G.823_1993的E3应用

控制并行微处理器接口和

CON组fi guration

会见抖动容限要求，规定

在符合Bellcore GR -499 -CORE的DS3应用

支持

监测

可选

国内

发送

司机

声明的锁（ LOL ）报警丢失

内置B3ZS / HDB3解码器（其可以是

禁用）

每个通道都支持模拟，远程和数字

环背

恢复的数据可以被静音，而LOS

条件声明

单3.3 V± 5 ％电源

5V电压的数字量输入

可提供420针TBGA耐热增强型

包

输出是单轨道或双轨道数据的

终端设备

2

XRT73R12

修订版1.0.3

十二通道E3 / DS3 / STS - 1线路接口单元

目录

一般DESCRIPTION.............................................................................................................. 1

A

PPLICATIONS

............................................................................................................................................................... 1

F

IGURE

1. B

LOCK

D

的作者IAGRAM

XRT 73R12 .................................................................................................................................... 1

订购信息.................................................................................................................... 1

F

EATURES

..................................................................................................................................................................... 2

T

RANSMIT

I

覆盖整个院落

C

极特

....................................................................................................................... 2

R

ECEIVE

I

覆盖整个院落

C

极特

......................................................................................................................... 2

引脚说明（按功能） ............................................ .............................................. 3

S

变体系

-S

IDE

T

RANSMIT

I

NPUT和

T

RANSMIT

C

ONTROL

P

插件

....................................................................................... 3

S

变体系

-S

IDE

R

ECEIVE

O

和安输出

R

ECEIVE

C

ONTROL

P

插件

....................................................................................... 6

R

ECEIVE

L

INE

S

IDE

P

插件

............................................................................................................................................... 8

C

LOCK

I

覆盖整个院落

......................................................................................................................................................... 9

G

ENERAL

C

ONTROL

P

插件

............................................................................................................................................ 10

P

OWER

S

UPPLY

P

插件

.................................................................................................................................................. 12

G

圆

P

插件

............................................................................................................................................................. 13

T

ABLE

1: L

IST BY

P

IN

N

棕土

............................................................................................................................................................. 14

功能说明...................................................................................................... 18

1.0 R3技术（可重构， RELAYLESS冗余） ....................................... 18

1.1网络架构......................................................................................................................... 18

F

IGURE

2. N

ETWORK

R

EDUNDANCY

A

体系结构的设计

.............................................................................................................................. 18

2.0时钟合成器....................................................................................................................... 19

F

IGURE

3. S

IMPLIFIED

B

LOCK

D

的作者IAGRAM

I

NPUT

C

LOCK

C

IRCUITRY

D

分料的

M

ICROPROCESSOR

............................................ 19

T

ABLE

2: R

指南

C

LOCK

P

ERFORMANCE

S

PECIFICATIONS

.............................................................................................................. 19

2.1时钟分配................................................................................................................................. 20

F

IGURE

4. C

LOCK

D

ISTRIBUTION

C

ONGIFURED IN

E3 M

ODE

W

ITHOUT

U

星

SFM ................................................. ............................... 20

3.0接收器部分.................................................................................................................. 21

F

IGURE

5. R

ECEIVE

P

ATH

B

LOCK

D

IAGRAM

.......................................................................................................................................... 21

3.1接收线路接口.......................................................................................................................... 21

F

IGURE

6. R

ECEIVE

L

INE

I

覆盖整个院落

C

ONNECTION

................................................................................................................................. 21

3.2自适应增益控制（AGC ） .............................................................................................................. 21

3.3接收均衡器................................................................................................................................... 21

F

IGURE

7. ACG / E

QUALIZER

B

LOCK

D

IAGRAM

....................................................................................................................................... 22

3.3.1建议FOR均衡器设置........................................... .................................................. 22

3.4时钟和数据恢复................................................................................................................... 22

3.4.1数据/时钟恢复模式............................................................................................................................ 22

3.4.2培训MODE........................................................................................................................................................ 22

3.5 LOS （信号丢失）检测仪........................................................................................................... 22

3.5.1 DS3 / STS - 1 LOS条件..................................................................................................................................... 22

T

ABLE

3: T

HE

ALOS （A

NALOG

LOS ）D

ECLARATION和

C

LEARANCE

T

HRESHOLDS对于一个给定的地点

REQEN （ DS3

和

STS - 1

P

-

并发症

).......................................................................................................................................................................... 23

3.5.2禁止ALOS / DLOS检测..................................................................................................................... 23

3.5.3 E3 LOS CONDITION:.................................................................................................................................................. 23

F

IGURE

8. L

OSS

O

F

S

IGNAL

D

EFINITION FOR

E3

按照

ITU -T G.775 ............................................ .................................................. .... 23

F

IGURE

9. L

开放源码软件

S

IGNAL

D

EFINITION FOR

E3

按照

ITU -T G.775................................................................................................... 24

3.5.4干扰TOLERANCE.................................................................................................................................. 24

F

IGURE

10. I

干涉现象

M

ARGIN

T

美东时间

S

ET UP FOR

DS3 / STS-1 ...................................................................................................... 24

F

IGURE

11. I

干涉现象

M

ARGIN

T

美东时间

S

ET UP FOR

E3. ................................................................................................................... 24

T

ABLE

4: I

干涉现象

M

ARGIN

T

美东时间

R

ESULTS

................................................................................................................................. 25

3.5.5静音带LOS情况恢复的数据： ....................................... ............................................ 25

F

IGURE

12. R

ECEIVER

D

ATA输出和违章时序

........................................................................................................ 25

3.6 B3ZS / HDB3解码器.................................................................................................................................. 26

4.0发射器部分........................................................................................................... 27

F

IGURE

13. T

RANSMIT

P

ATH

B

LOCK

D

IAGRAM

...................................................................................................................................... 27

4.1传输数字输入接口..................................................................................................... 27

F

IGURE

14. T

终端之间的设备和YPICAL界面

XRT73R12 （

双

-

RAIL数据

) .............................................. 27

F

IGURE

15. T

变送器

T

端子

I

NPUT

T

即时通信

............................................................................................................................... 28

F

IGURE

16. S

炉火

-R

AIL或

NRZ

ATA

F

ORMAT

(E

NCODER和

D

ECODER ARE

E

NABLED

) .................................................................. 28

4.2发送时钟........................................................................................................................................ 29

4.3 B3ZS / HDB3编码器.................................................................................................................................. 29

4.3.1 B3ZS编码....................................................................................................................................................... 29

I

XRT73R12

十二通道E3 / DS3 / STS - 1线路接口单元

修订版1.0.3

F

IGURE

18. B3ZS ê

NCODING

F

ORMAT

................................................................................................................................................. 29

4.3.2 HDB3编码....................................................................................................................................................... 29

F

IGURE

17. D

UAL

-R

AIL

D

ATA

F

ORMAT

(

编码器和解码器将被禁用

).................................................................................... 29

F

IGURE

19. HDB3 ê

NCODING

F

ORMAT

................................................................................................................................................. 30

4.4 TRANSMIT脉冲整形.........................................................................................................................三十

F

IGURE

20. T

RANSMIT

P

ULSE

S

高原肺水肿

T

美东时间

C

IRCUIT

.............................................................................................................................. 30

4.4.1准则使用发送打造出电路........................................ .......................................... 30

4.5 E3线路侧参数........................................................................................................................ 31

F

IGURE

21. P

ULSE

M

征求

E3 (34.368

兆位

/

S

)

接口符合ITU

-

T

G.703 ............................................................................. 31

T

ABLE

5 ： E3牛逼

变送器线路侧器输出和接收线路侧输入规范

.............................................................. 32

F

IGURE

22. B

ELLCORE

GR - 253心T

RANSMIT

O

安输出

P

ULSE

T

EMPLATE FOR

SONET STS - 1

PPLICATIONS

................................. 33

T

ABLE

6 ： STS -1 P

ULSE

M

ASK

E

QUATIONS

........................................................................................................................................... 33

T

ABLE

7 ： STS - 1 T＆

变送器

L

INE

S

IDE

O

和安输出

R

ECEIVER

L

INE

S

IDE

I

NPUT

S

PECIFICATIONS

（ GR- 253 ） ..................................... 34

F

IGURE

23. T

RANSMIT

O

UPUT

P

ULSE

T

EMPLATE FOR

DS3

按照

B

ELLCORE

GR- 499 ............................................... .......................... 34

T

ABLE

8 ： DS3 P

ULSE

M

ASK

E

QUATIONS

............................................................................................................................................... 35

T

ABLE

9 ： DS3牛逼

变送器

L

INE

S

IDE

O

和安输出

R

ECEIVER

L

INE

S

IDE

I

NPUT

S

PECIFICATIONS

（ GR- 499 ） ........................................ 35

4.6传递驱动MONITOR ........................................................................................................................ 36

F

IGURE

24. T

RANSMIT

D

河

M

ONITOR SET

-

UP

................................................................................................................................... 36

4.7发射器部分的ON / OFF ............................................................................................................... 36

5.0抖动..................................................................................................................................................37

5.1抖动容限..................................................................................................................................... 37

F

IGURE

25. J

伊特尔

T

OLERANCE

M

EASUREMENTS

.................................................................................................................................. 37

5.1.1 DS3 / STS - 1的抖动容限要求....................................... .................................................. ....... 37

F

IGURE

26. I

NPUT

J

伊特尔

T

OLERANCE

F

OR

DS3 / STS-1 ...................................................................................................................... 38

5.1.2 E3抖动容限要求.............................................................................................................. 38

F

IGURE

27. I

NPUT

J

伊特尔

T

OLERANCE FOR

E3..................................................................................................................................... 38

T

ABLE

10: J

伊特尔

A

MPLITUDE VERSUS

M

ODULATION

F

Characteristic低频

(J

伊特尔

T

OLERANCE

) ......................................................................... 39

5.2抖动转移........................................................................................................................................ 39

T

ABLE

11: J

伊特尔

T

转让（BOT）

S

PECIFICATION

/R

EFERENCES

................................................................................................................... 39

T

ABLE

12: J

伊特尔

T

转让（BOT）

P

屁股

M

ASKS

........................................................................................................................................... 39

F

IGURE

28. J

伊特尔

T

转让（BOT）

R

EQUIREMENTS

..................................................................................................................................... 40

5.2.1抖动GENERATION................................................................................................................................................ 40

6.0诊断功能...................................................................................................................41

6.1 PRBS发生器和检测......................................................................................................... 41

F

IGURE

29. PRBS模式................................................................................................................................................................... 41

6.2环回.................................................................................................................................................. 42

6.2.1模拟环回................................................................................................................................................ 42

F

IGURE

30. A

NALOG

L

OOPBACK

........................................................................................................................................................... 42

6.2.2数字环................................................................................................................................................. 43

F

IGURE

31. D

IGITAL

L

OOPBACK

............................................................................................................................................................ 43

6.2.3远方返回................................................................................................................................................ 43

F

IGURE

32. R

EMOTE

L

OOPBACK

........................................................................................................................................................... 43

6.3传输所有ONES （ TAOS ） ...................................................................................................................... 44

F

IGURE

33. T

RANSMIT

A

LL

O

NES

（ TAOS ） ............................................................................................................................................ 44

7.0微处理器接口模块.............................................. .......................................... 45

T

ABLE

13: S

选举

M

ICROPROCESSOR

I

覆盖整个院落

M

ODE

.......................................................................................................... 45

F

IGURE

34. S

IMPLIFIED

B

LOCK

D

的作者IAGRAM

M

ICROPROCESSOR

I

覆盖整个院落

B

LOCK

........................................................................ 45

7.1微处理器接口闭塞信号............................................ ............................. 46

T

ABLE

14 ： XRT73R12 M

ICROPROCESSOR

I

覆盖整个院落

S

IGNALS

............................................................................................................ 46

7.2异步和同步说明............................................. ............................. 47

F

IGURE

35. A

同步

我μP

覆盖整个院落

S

IGNALS

D

URING

P

ROGRAMMED

I / O

EAD和

W

RITE

O

PERATIONS

.................................. 47

T

ABLE

15: A

同步

T

即时通信

S

PECIFICATIONS

............................................................................................................................. 48

F

IGURE

36. S

YNCHRONOUS

我μP

覆盖整个院落

S

IGNALS

D

URING

P

ROGRAMMED

I / O

EAD和

W

RITE

O

PERATIONS

.................................... 48

T

ABLE

16: S

YNCHRONOUS

T

即时通信

S

PECIFICATIONS

............................................................................................................................... 48

7.3寄存器映射............................................................................................................................................. 49

T

ABLE

17:

C

OMMAND

R

EGISTER

A

地址H1

M

AP

,

WITHIN THE

XRT73R12 ................................................. ........................................... 49

全球/芯片级寄存器................................................................................................................ 58

T

ABLE

18: L

IST和

A

地址H1

L

作者OCATIONS

G

叶形

R

EGISTERS

........................................................................................................ 58

................................................................................................................................................................................... 58

................................................................................................................................................................................... 58

寄存器描述 - 全局寄存器............................................. .................................................. 58

T

ABLE

19 ： APS / R

EDUNDANCY

T

RANSMIT

C

ONTROL

R

EGISTER

- CR0 （A

地址H1

L

OCATION

= 0

X

00) ..................................................... 58

T

ABLE

20 ： APS / R

EDUNDANCY

R

ECEIVE

C

ONTROL

R

EGISTER

- CR8 （A

地址H1

L

OCATION

= 0

X

08) ....................................................... 59

T

ABLE

21 ： APS / R

EDUNDANCY

T

RANSMIT

C

ONTROL

R

EGISTER

- CR128 （A

地址H1

L

OCATION

= 0

X

80) ................................................. 59

II

XRT73R12

修订版1.0.3

十二通道E3 / DS3 / STS - 1线路接口单元

T

ABLE

22 ： APS / R

EDUNDANCY

R

ECEIVE

C

ONTROL

R

EGISTER

- CR136 （A

地址H1

L

OCATION

= 0

X

88) ................................................... 60

F

IGURE

37. C

HANNEL

L

伊维尔基尼

I

NTERRUPT

E

NABLE

R

EGISTER

- CR96 （A

地址H1

L

OCATION

= 0

X

60) ....................................................... 61

T

ABLE

23: C

HANNEL

L

伊维尔基尼

I

NTERRUPT

E

NABLE

R

EGISTER

- CR224 （A

地址H1

L

OCATION

= 0

X

E0........................................................ 62

T

ABLE

24: C

HANNEL

L

伊维尔基尼

I

NTERRUPT

S

TATUS

R

EGISTER

- CR97 （A

地址H1

L

OCATION

= 0

X

61) ......................................................... 63

.................................................................................................................................................................................. 63

T

ABLE

25: C

HANNEL

L

伊维尔基尼

I

NTERRUPT

S

TATUS

R

EGISTER

- CR225 （A

地址H1

L

OCATION

= 0

X

E1)....................................................... 64

T

ABLE

26: D

EVICE

/P

艺术

N

棕土

R

EGISTER

- CR110 （A

地址H1

L

OCATION

= 0

X

6E) ........................................................................... 64

T

ABLE

27: C

HIP

R

EVISION

N

棕土

R

EGISTER

- CR111 （A

地址H1

L

OCATION

= 0

X

6F) ......................................................................... 65

每通道REGISTERS........................................................................................................................... 66

寄存器描述 - 每个通道寄存器............................................ ........................................ 66

T

ABLE

28:

T

ABLE

29:

T

ABLE

30:

T

ABLE

31:

T

ABLE

32:

T

ABLE

33:

T

ABLE

34:

T

ABLE

35:

T

ABLE

36:

T

ABLE

37:

T

ABLE

38:

T

ABLE

39:

T

ABLE

40:

T

ABLE

41:

T

ABLE

42:

T

ABLE

43:

T

ABLE

44:

T

ABLE

45:

XRT73R12

EGISTER

地图

展示

I

NTERRUPT

E

NABLE

R

EGISTERS

（ IER_

N

) (

N

= [0:11]) ............................................... 66

S

环境允许

L

伊维尔基尼

I

NTERRUPT

E

NABLE

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

1 .................................................... 67

XRT73R12

EGISTER

地图

展示

I

NTERRUPT

S

TATUS

R

EGISTERS

（ ISR_

N

).................................................................. 68

S

环境允许

L

伊维尔基尼

I

NTERRUPT

S

TATUS

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

2 .................................................... 68

XRT73R12

EGISTER

地图

展示

A

LARM

S

TATUS

R

EGISTERS

（附上as_

N

) .......................................................................... 70

A

LARM

S

TATUS

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

3................................................................................... 70

XRT73R12

EGISTER

地图

展示

T

RANSMIT

C

ONTROL

R

EGISTERS

（ TC_

N

)................................................................... 73

T

RANSMIT

C

ONTROL

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

4 ........................................................................... 73

XRT73R12

EGISTER

地图

展示

R

ECEIVE

C

ONTROL

R

EGISTERS

（ RC_

N

) .................................................................... 75

R

ECEIVE

C

ONTROL

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

5 ............................................................................. 75

XRT73R12

EGISTER

地图

展示

C

HANNEL

C

ONTROL

R

EGISTERS

(CC_

N

) ................................................................... 77

C

HANNEL

C

ONTROL

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

6 ............................................................................ 77

XRT73R12

EGISTER

地图

展示

E

RROR

C

OUNTER

最高位

YTE

R

EGISTERS

（ EM_

N

) (

N

= [0:11]) ..................................... 80

E

RROR

C

OUNTER

最高位

YTE

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

A (

M

= 0-5 & 8 - D） ........................................ 80

XRT73R12

EGISTER

地图

展示

E

RROR

C

OUNTER

最低位

YTE

R

EGISTERS

（ EL_

N

) (

N

= [0:11]) ....................................... 80

E

RROR

C

OUNTER

最低位

YTE

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

B (

M

= 0-5 & 8 -D ） ......................................... 81

XRT73R12

EGISTER

地图

展示

E

RROR

C

OUNTER

H

掩门

R

EGISTERS

（ EH_

N

) (

N

= [0:11]) ..................................... 81

E

RROR

C

OUNTER

H

掩门

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

C (

M

= 0-5 & 8 - D） ........................................ 82

8.0电气特性............................................... .................................................. .. 83

T

ABLE

46: A

BSOLUTE

M

AXIMUM

R

ATINGS

............................................................................................................................................. 83

T

ABLE

47 ： DC é

LECTRICAL

C

极特

:..................................................................................................................................... 84

订购信息.................................................................................................................. 85

P

ACKAGE

D

IMENSIONS

- .............................................................................................................................................. 85

R

EVISION

H

ISTORY

...................................................................................................................................................... 86

III

XRT73R12

十二通道E3 / DS3 / STS - 1线路接口单元

2007年6月

修订版1.0.2

概述

该XRT73R12是一个12通道的完全集成

线路接口单元（LIU ），具有Exar的

3

技术（可重构， Relayless冗余）

对于E3 / DS3 / STS - 1的应用程序。刘整合

在12个独立的接收器和发射器

单420铅TBGA封装。

在XRT73R12的每个通道可

独立配置的E3操作（ 34.368

兆赫） ，DS3 （ 44.736兆赫）或STS -1（ 51.84兆赫） 。

每个发射器可以被关闭，并且三态

冗余支持或节省电力。

该XRT73R12的差分接收器提供了高

噪声干扰余量，并且能够接收数据

超过1000英尺的电缆或电缆的高达12分贝

衰减。

F

IGURE

1. B

LOCK

D

的作者IAGRAM

XRT 73R12

该XRT73R12提供了一个并行微处理器

接口进行编程和控制。

该XRT73R12支持模拟，远程和数字

环边后卫。该设备还具有一个内置的伪

随机二进制序列（ PRBS ）发生器和

检测器与插入和检测单个位的能力

错误诊断目的。

应用

E3 / DS3接入设备

DSLAM设备

数字交叉连接系统

CSU / DSU设备

路由器

光纤终端

CS

RD

WR

ADDR [ 7：0]

D[7:0]

PCLK

RDY

INT

PMODE

RESET

XRT73R12

CLKOUT_n

μprocessor

接口

SFM_EN

RLOL_n

E3Clk

DS3Clk

STS-Clk/12M

MUX

峰值检波器

切片机

时钟&数据

恢复

LOS

探测器

时钟

合成

HDB3/

B3ZS

解码器

RxClk_n

RxPOS_n

RxNEG / LCV_n

RTIP_n

RRING_n

AGC /

均衡器

当地

环回

远程

环回

RLOS_n

TxClk_n

TxPOS_n

TxNEG_n

TTIP_n

TRING_n

MTIP_n

MRing_n

DMO_n

信息和通信技术

LINE

司机

Tx

脉冲

成型

定时

控制

MUX

HDB3/

B3ZS

编码器

设备

MONITOR

Tx

控制

TXON

通道0

通道n ...

CHANNEL 11

订购信息

P

艺术

N

棕土

XRT73R12IB

P

ACKAGE

420铅TBGA

O

操作摄像机

T

emperature

R

ANGE

-40

°

C至+ 85

°

C

Exar公司

公司48720加藤道，弗里蒙特CA， 94538

(510) 668-7000

传真（ 510 ） 668-7017

www.exar.com

XRT73R12

十二通道E3 / DS3 / STS - 1线路接口单元

修订版1.0.2

特点

接收器

- 40 ° C至85°C工业级温度范围

发送接口特性

（可重构，

Relayless

R

3

技术

冗余）

输入抖动容限

接受来自任何单轨或双轨数据

终端设备，并产生一个双极性信号

到行

片上时钟和数据恢复电路高

会见E3 / DS3 / STS - 1抖动容限要求

检测并清除LOS按G.775

接收监控模式处理多达20分贝平

与6分贝电缆的衰减损耗

集成的脉冲整形电路

内置B3ZS / HDB3编码器（其可以是

禁用）

接受发送时钟为30％占空比 -

70%

芯片B3ZS / HDB3编码器和解码器，可

可以启用或禁用

生成符合ITU -T G.703脉冲

对于E3应用脉冲模板

片上时钟合成器提供适当的

从单一12.288 MHz的时钟速率时钟

生成符合DSX - 3脉冲的脉冲

模板，如在符合Bellcore GR -499中指定

-core

和ANSI T1.102_1993

提供低抖动输出时钟

发射机

生成符合STSX - 1脉冲

脉冲模板，如在Bellcore的指定GR- 253-

CORE

Relayless

R

3

技术

冗余）

（可重构，

发射机可以以支持被关闭

冗余设计

接收接口特性

符合符合Bellcore GR - 499 ， GR- 253和ANSI

T1.102规范发射脉冲

三态的冗余发送输出能力

应用

集成自适应接收均衡（可选）

最佳的时钟和数据恢复

每个发射器可以被独立地接通

或OFF

声明并清除按照ITU-T的LOS缺陷

为E3和DS3应用G.775的要求

变送器提供电压输出驱动器

控制和诊断

会见抖动容限要求，规定

在ITU -T G.823_1993的E3应用

控制并行微处理器接口和

CON组fi guration

会见抖动容限要求，规定

在符合Bellcore GR -499 -CORE的DS3应用

支持

监测

可选

国内

发送

司机

声明的锁（ LOL ）报警丢失

内置B3ZS / HDB3解码器（其可以是

禁用）

每个通道都支持模拟，远程和数字

环背

恢复的数据可以被静音，而LOS

条件声明

单3.3 V± 5 ％电源

5V电压的数字量输入

可提供420针TBGA耐热增强型

包

输出是单轨道或双轨道数据的

终端设备

2

XRT73R12

修订版1.0.2

十二通道E3 / DS3 / STS - 1线路接口单元

目录

一般DESCRIPTION.............................................................................................................. 1

A

PPLICATIONS

............................................................................................................................................................... 1

F

IGURE

1. B

LOCK

D

的作者IAGRAM

XRT 73R12 .................................................................................................................................... 1

订购信息.................................................................................................................... 1

F

EATURES

..................................................................................................................................................................... 2

T

RANSMIT

I

覆盖整个院落

C

极特

....................................................................................................................... 2

R

ECEIVE

I

覆盖整个院落

C

极特

......................................................................................................................... 2

引脚说明（按功能） ............................................ .............................................. 3

S

变体系

-S

IDE

T

RANSMIT

I

NPUT和

T

RANSMIT

C

ONTROL

P

插件

....................................................................................... 3

S

变体系

-S

IDE

R

ECEIVE

O

和安输出

R

ECEIVE

C

ONTROL

P

插件

....................................................................................... 6

R

ECEIVE

L

INE

S

IDE

P

插件

............................................................................................................................................... 8

C

LOCK

I

覆盖整个院落

......................................................................................................................................................... 9

G

ENERAL

C

ONTROL

P

插件

............................................................................................................................................ 10

P

OWER

S

UPPLY

P

插件

.................................................................................................................................................. 12

G

圆

P

插件

............................................................................................................................................................. 13

T

ABLE

1: L

IST BY

P

IN

N

棕土

............................................................................................................................................................. 14

功能说明...................................................................................................... 18

1.0 R3技术（可重构， RELAYLESS冗余） ....................................... 18

1.1网络架构......................................................................................................................... 18

F

IGURE

2. N

ETWORK

R

EDUNDANCY

A

体系结构的设计

.............................................................................................................................. 18

2.0时钟合成器....................................................................................................................... 19

F

IGURE

3. S

IMPLIFIED

B

LOCK

D

的作者IAGRAM

I

NPUT

C

LOCK

C

IRCUITRY

D

分料的

M

ICROPROCESSOR

............................................ 19

T

ABLE

2: R

指南

C

LOCK

P

ERFORMANCE

S

PECIFICATIONS

.............................................................................................................. 19

2.1时钟分配................................................................................................................................. 20

F

IGURE

4. C

LOCK

D

ISTRIBUTION

C

ONGIFURED IN

E3 M

ODE

W

ITHOUT

U

星

SFM ................................................. ............................... 20

3.0接收器部分.................................................................................................................. 21

F

IGURE

5. R

ECEIVE

P

ATH

B

LOCK

D

IAGRAM

.......................................................................................................................................... 21

3.1接收线路接口.......................................................................................................................... 21

F

IGURE

6. R

ECEIVE

L

INE

I

覆盖整个院落

C

ONNECTION

................................................................................................................................. 21

3.2自适应增益控制（AGC ） .............................................................................................................. 21

3.3接收均衡器................................................................................................................................... 21

F

IGURE

7. ACG / E

QUALIZER

B

LOCK

D

IAGRAM

....................................................................................................................................... 22

3.3.1建议FOR均衡器设置........................................... .................................................. 22

3.4时钟和数据恢复................................................................................................................... 22

3.4.1数据/时钟恢复模式............................................................................................................................ 22

3.4.2培训MODE........................................................................................................................................................ 22

3.5 LOS （信号丢失）检测仪........................................................................................................... 22

3.5.1 DS3 / STS - 1 LOS条件..................................................................................................................................... 22

T

ABLE

3: T

HE

ALOS （A

NALOG

LOS ）D

ECLARATION和

C

LEARANCE

T

HRESHOLDS对于一个给定的地点

REQEN （ DS3

和

STS - 1

P

-

并发症

).......................................................................................................................................................................... 23

3.5.2禁止ALOS / DLOS检测..................................................................................................................... 23

3.5.3 E3 LOS CONDITION:.................................................................................................................................................. 23

F

IGURE

8. L

OSS

O

F

S

IGNAL

D

EFINITION FOR

E3

按照

ITU -T G.775 ............................................ .................................................. .... 23

F

IGURE

9. L

开放源码软件

S

IGNAL

D

EFINITION FOR

E3

按照

ITU -T G.775................................................................................................... 24

3.5.4干扰TOLERANCE.................................................................................................................................. 24

F

IGURE

10. I

干涉现象

M

ARGIN

T

美东时间

S

ET UP FOR

DS3 / STS-1 ...................................................................................................... 24

F

IGURE

11. I

干涉现象

M

ARGIN

T

美东时间

S

ET UP FOR

E3. ................................................................................................................... 24

T

ABLE

4: I

干涉现象

M

ARGIN

T

美东时间

R

ESULTS

................................................................................................................................. 25

3.5.5静音带LOS情况恢复的数据： ....................................... ............................................ 25

F

IGURE

12. R

ECEIVER

D

ATA输出和违章时序

........................................................................................................ 25

3.6 B3ZS / HDB3解码器.................................................................................................................................. 26

4.0发射器部分........................................................................................................... 27

F

IGURE

13. T

RANSMIT

P

ATH

B

LOCK

D

IAGRAM

...................................................................................................................................... 27

4.1传输数字输入接口..................................................................................................... 27

F

IGURE

14. T

终端之间的设备和YPICAL界面

XRT73R12 （

双

-

RAIL数据

) .............................................. 27

F

IGURE

15. T

变送器

T

端子

I

NPUT

T

即时通信

............................................................................................................................... 28

F

IGURE

16. S

炉火

-R

AIL或

NRZ

ATA

F

ORMAT

(E

NCODER和

D

ECODER ARE

E

NABLED

) .................................................................. 28

4.2发送时钟........................................................................................................................................ 29

4.3 B3ZS / HDB3编码器.................................................................................................................................. 29

4.3.1 B3ZS编码....................................................................................................................................................... 29

I

XRT73R12

十二通道E3 / DS3 / STS - 1线路接口单元

修订版1.0.2

F

IGURE

18. B3ZS ê

NCODING

F

ORMAT

................................................................................................................................................. 29

4.3.2 HDB3编码....................................................................................................................................................... 29

F

IGURE

17. D

UAL

-R

AIL

D

ATA

F

ORMAT

(

编码器和解码器将被禁用

).................................................................................... 29

F

IGURE

19. HDB3 ê

NCODING

F

ORMAT

................................................................................................................................................. 30

4.4 TRANSMIT脉冲整形.........................................................................................................................三十

F

IGURE

20. T

RANSMIT

P

ULSE

S

高原肺水肿

T

美东时间

C

IRCUIT

.............................................................................................................................. 30

4.4.1准则使用发送打造出电路........................................ .......................................... 30

4.5 E3线路侧参数........................................................................................................................ 31

F

IGURE

21. P

ULSE

M

征求

E3 (34.368

兆位

/

S

)

接口符合ITU

-

T

G.703 ............................................................................. 31

T

ABLE

5 ： E3牛逼

变送器线路侧器输出和接收线路侧输入规范

.............................................................. 32

F

IGURE

22. B

ELLCORE

GR - 253心T

RANSMIT

O

安输出

P

ULSE

T

EMPLATE FOR

SONET STS - 1

PPLICATIONS

................................. 33

T

ABLE

6 ： STS -1 P

ULSE

M

ASK

E

QUATIONS

........................................................................................................................................... 33

T

ABLE

7 ： STS - 1 T＆

变送器

L

INE

S

IDE

O

和安输出

R

ECEIVER

L

INE

S

IDE

I

NPUT

S

PECIFICATIONS

（ GR- 253 ） ..................................... 34

F

IGURE

23. T

RANSMIT

O

UPUT

P

ULSE

T

EMPLATE FOR

DS3

按照

B

ELLCORE

GR- 499 ............................................... .......................... 34

T

ABLE

8 ： DS3 P

ULSE

M

ASK

E

QUATIONS

............................................................................................................................................... 35

T

ABLE

9 ： DS3牛逼

变送器

L

INE

S

IDE

O

和安输出

R

ECEIVER

L

INE

S

IDE

I

NPUT

S

PECIFICATIONS

（ GR- 499 ） ........................................ 35

4.6传递驱动MONITOR ........................................................................................................................ 36

F

IGURE

24. T

RANSMIT

D

河

M

ONITOR SET

-

UP

................................................................................................................................... 36

4.7发射器部分的ON / OFF ............................................................................................................... 36

5.0抖动..................................................................................................................................................37

5.1抖动容限..................................................................................................................................... 37

F

IGURE

25. J

伊特尔

T

OLERANCE

M

EASUREMENTS

.................................................................................................................................. 37

5.1.1 DS3 / STS - 1的抖动容限要求....................................... .................................................. ....... 37

F

IGURE

26. I

NPUT

J

伊特尔

T

OLERANCE

F

OR

DS3 / STS-1 ...................................................................................................................... 38

5.1.2 E3抖动容限要求.............................................................................................................. 38

F

IGURE

27. I

NPUT

J

伊特尔

T

OLERANCE FOR

E3..................................................................................................................................... 38

T

ABLE

10: J

伊特尔

A

MPLITUDE VERSUS

M

ODULATION

F

Characteristic低频

(J

伊特尔

T

OLERANCE

) ......................................................................... 39

5.2抖动转移........................................................................................................................................ 39

T

ABLE

11: J

伊特尔

T

转让（BOT）

S

PECIFICATION

/R

EFERENCES

................................................................................................................... 39

T

ABLE

12: J

伊特尔

T

转让（BOT）

P

屁股

M

ASKS

........................................................................................................................................... 39

F

IGURE

28. J

伊特尔

T

转让（BOT）

R

EQUIREMENTS

..................................................................................................................................... 40

5.2.1抖动GENERATION................................................................................................................................................ 40

6.0诊断功能...................................................................................................................41

6.1 PRBS发生器和检测......................................................................................................... 41

F

IGURE

29. PRBS模式................................................................................................................................................................... 41

6.2环回.................................................................................................................................................. 42

6.2.1模拟环回................................................................................................................................................ 42

F

IGURE

30. A

NALOG

L

OOPBACK

........................................................................................................................................................... 42

6.2.2数字环................................................................................................................................................. 43

F

IGURE

31. D

IGITAL

L

OOPBACK

............................................................................................................................................................ 43

6.2.3远方返回................................................................................................................................................ 43

F

IGURE

32. R

EMOTE

L

OOPBACK

........................................................................................................................................................... 43

6.3传输所有ONES （ TAOS ） ...................................................................................................................... 44

F

IGURE

33. T

RANSMIT

A

LL

O

NES

（ TAOS ） ............................................................................................................................................ 44

7.0微处理器接口模块.............................................. .......................................... 45

T

ABLE

13: S

选举

M

ICROPROCESSOR

I

覆盖整个院落

M

ODE

.......................................................................................................... 45

F

IGURE

34. S

IMPLIFIED

B

LOCK

D

的作者IAGRAM

M

ICROPROCESSOR

I

覆盖整个院落

B

LOCK

........................................................................ 45

7.1微处理器接口闭塞信号............................................ ............................. 46

T

ABLE

14 ： XRT73R12 M

ICROPROCESSOR

I

覆盖整个院落

S

IGNALS

............................................................................................................ 46

7.2异步和同步说明............................................. ............................. 47

F

IGURE

35. A

同步

我μP

覆盖整个院落

S

IGNALS

D

URING

P

ROGRAMMED

I / O

EAD和

W

RITE

O

PERATIONS

.................................. 47

T

ABLE

15: A

同步

T

即时通信

S

PECIFICATIONS

............................................................................................................................. 48

F

IGURE

36. S

YNCHRONOUS

我μP

覆盖整个院落

S

IGNALS

D

URING

P

ROGRAMMED

I / O

EAD和

W

RITE

O

PERATIONS

.................................... 48

T

ABLE

16: S

YNCHRONOUS

T

即时通信

S

PECIFICATIONS

............................................................................................................................... 48

7.3寄存器映射............................................................................................................................................. 49

T

ABLE

17:

C

OMMAND

R

EGISTER

A

地址H1

M

AP

,

WITHIN THE

XRT73R12 ................................................. ........................................... 49

全球/芯片级寄存器................................................................................................................ 58

T

ABLE

18: L

IST和

A

地址H1

L

作者OCATIONS

G

叶形

R

EGISTERS

........................................................................................................ 58

................................................................................................................................................................................... 58

................................................................................................................................................................................... 58

寄存器描述 - 全局寄存器............................................. .................................................. 58

T

ABLE

19 ： APS / R

EDUNDANCY

T

RANSMIT

C

ONTROL

R

EGISTER

- CR0 （A

地址H1

L

OCATION

= 0

X

00) ..................................................... 58

T

ABLE

20 ： APS / R

EDUNDANCY

R

ECEIVE

C

ONTROL

R

EGISTER

- CR8 （A

地址H1

L

OCATION

= 0

X

08) ....................................................... 59

T

ABLE

21 ： APS / R

EDUNDANCY

T

RANSMIT

C

ONTROL

R

EGISTER

- CR128 （A

地址H1

L

OCATION

= 0

X

80) ................................................. 59

II

XRT73R12

修订版1.0.2

十二通道E3 / DS3 / STS - 1线路接口单元

T

ABLE

22 ： APS / R

EDUNDANCY

R

ECEIVE

C

ONTROL

R

EGISTER

- CR136 （A

地址H1

L

OCATION

= 0

X

88) ................................................... 60

F

IGURE

37. C

HANNEL

L

伊维尔基尼

I

NTERRUPT

E

NABLE

R

EGISTER

- CR96 （A

地址H1

L

OCATION

= 0

X

60) ....................................................... 61

T

ABLE

23: C

HANNEL

L

伊维尔基尼

I

NTERRUPT

E

NABLE

R

EGISTER

- CR224 （A

地址H1

L

OCATION

= 0

X

E0........................................................ 62

T

ABLE

24: C

HANNEL

L

伊维尔基尼

I

NTERRUPT

S

TATUS

R

EGISTER

- CR97 （A

地址H1

L

OCATION

= 0

X

61) ......................................................... 63

.................................................................................................................................................................................. 63

T

ABLE

25: C

HANNEL

L

伊维尔基尼

I

NTERRUPT

S

TATUS

R

EGISTER

- CR225 （A

地址H1

L

OCATION

= 0

X

E1)....................................................... 64

T

ABLE

26: D

EVICE

/P

艺术

N

棕土

R

EGISTER

- CR110 （A

地址H1

L

OCATION

= 0

X

6E) ........................................................................... 64

T

ABLE

27: C

HIP

R

EVISION

N

棕土

R

EGISTER

- CR111 （A

地址H1

L

OCATION

= 0

X

6F) ......................................................................... 65

每通道REGISTERS........................................................................................................................... 66

寄存器描述 - 每个通道寄存器............................................ ........................................ 66

T

ABLE

28:

T

ABLE

29:

T

ABLE

30:

T

ABLE

31:

T

ABLE

32:

T

ABLE

33:

T

ABLE

34:

T

ABLE

35:

T

ABLE

36:

T

ABLE

37:

T

ABLE

38:

T

ABLE

39:

T

ABLE

40:

T

ABLE

41:

T

ABLE

42:

T

ABLE

43:

T

ABLE

44:

T

ABLE

45:

XRT73R12

EGISTER

地图

展示

I

NTERRUPT

E

NABLE

R

EGISTERS

（ IER_

N

) (

N

= [0:11]) ............................................... 66

S

环境允许

L

伊维尔基尼

I

NTERRUPT

E

NABLE

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

1 .................................................... 67

XRT73R12

EGISTER

地图

展示

I

NTERRUPT

S

TATUS

R

EGISTERS

（ ISR_

N

).................................................................. 68

S

环境允许

L

伊维尔基尼

I

NTERRUPT

S

TATUS

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

2 .................................................... 68

XRT73R12

EGISTER

地图

展示

A

LARM

S

TATUS

R

EGISTERS

（附上as_

N

) .......................................................................... 70

A

LARM

S

TATUS

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

3................................................................................... 70

XRT73R12

EGISTER

地图

展示

T

RANSMIT

C

ONTROL

R

EGISTERS

（ TC_

N

)................................................................... 73

T

RANSMIT

C

ONTROL

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

4 ........................................................................... 73

XRT73R12

EGISTER

地图

展示

R

ECEIVE

C

ONTROL

R

EGISTERS

（ RC_

N

) .................................................................... 75

R

ECEIVE

C

ONTROL

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

5 ............................................................................. 75

XRT73R12

EGISTER

地图

展示

C

HANNEL

C

ONTROL

R

EGISTERS

(CC_

N

) ................................................................... 77

C

HANNEL

C

ONTROL

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

6 ............................................................................ 77

XRT73R12

EGISTER

地图

展示

E

RROR

C

OUNTER

最高位

YTE

R

EGISTERS

（ EM_

N

) (

N

= [0:11]) ..................................... 80

E

RROR

C

OUNTER

最高位

YTE

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

A (

M

= 0-5 & 8 - D） ........................................ 80

XRT73R12

EGISTER

地图

展示

E

RROR

C

OUNTER

最低位

YTE

R

EGISTERS

（ EL_

N

) (

N

= [0:11]) ....................................... 80

E

RROR

C

OUNTER

最低位

YTE

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

B (

M

= 0-5 & 8 -D ） ......................................... 81

XRT73R12

EGISTER

地图

展示

E

RROR

C

OUNTER

H

掩门

R

EGISTERS

（ EH_

N

) (

N

= [0:11]) ..................................... 81

E

RROR

C

OUNTER

H

掩门

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

C (

M

= 0-5 & 8 - D） ........................................ 82

8.0电气特性............................................... .................................................. .. 83

T

ABLE

46: A

BSOLUTE

M

AXIMUM

R

ATINGS

............................................................................................................................................. 83

T

ABLE

47 ： DC é

LECTRICAL

C

极特

:..................................................................................................................................... 84

订购信息.................................................................................................................. 85

P

ACKAGE

D

IMENSIONS

- .............................................................................................................................................. 85

R

EVISION

H

ISTORY

...................................................................................................................................................... 86

III

初步

2003年10月

XRT73R12

REV 。 P1.0.3

十二通道E3 / DS3 / STS - 1线路接口单元

概述

该XRT73R12是一个12通道的完全集成

线路接口单元（LIU ），具有Exar的

3

技术（可重构， Relayless冗余）

对于E3 / DS3 / STS - 1的应用程序。刘整合

在12个独立的接收器和发射器

单420铅TBGA封装。

在XRT73R12的每个通道可

独立配置的E3操作（ 34.368

兆赫） ，DS3 （ 44.736兆赫）或STS -1（ 51.84兆赫） 。

每个发射器可以被关闭，并且三态

冗余支持或节省电力。

该XRT73R12的差分接收器提供了高

噪声干扰余量，并且能够接收数据

超过1000英尺的电缆或电缆的高达12分贝

衰减。

该XRT73R12提供了一个并行微处理器

接口进行编程和控制。

该XRT73R12支持模拟，远程和数字

环边后卫。该设备还具有一个内置的伪

随机二进制序列（ PRBS ）发生器和

检测器与插入和检测单个位的能力

错误诊断目的。

应用

E3 / DS3接入设备

DSLAM设备

数字交叉连接系统

CSU / DSU设备

路由器

光纤终端

F

IGURE

1. B

LOCK

D

的作者IAGRAM

XRT 73R12

CS

RD

WR

ADDR [ 7：0]

D[7:0]

PCLK

RDY

INT

PMODE

RESET

XRT73R12

CLKOUT_n

μprocessor

接口

SFM_EN

RLOL_n

E3Clk

DS3Clk

STS-Clk/12M

MUX

峰值检波器

切片机

时钟&数据

恢复

LOS

探测器

时钟

合成

HDB3/

B3ZS

解码器

RTIP_n

RRING_n

AGC /

均衡器

RxClk_n

RxPOS_n

RxNEG / LCV_n

当地

环回

远程

环回

RLOS_n

TxClk_n

TxPOS_n

TxNEG_n

TTIP_n

TRING_n

MTIP_n

MRing_n

DMO_n

信息和通信技术

LINE

司机

Tx

脉冲

成型

定时

控制

MUX

HDB3/

B3ZS

编码器

设备

MONITOR

Tx

控制

TXON

通道0

通道n ...

CHANNEL 11

订购信息

P

艺术

N

棕土

XRT73R12IB

P

ACKAGE

420铅TBGA

O

操作摄像机

T

emperature

R

ANGE

-40

°

C至+ 85

°

C

Exar公司

公司48720加藤道，弗里蒙特CA， 94538

(510) 668-7000

传真（ 510 ） 668-7017

www.exar.com

XRT73R12

REV 。 P1.0.3

初步

十二通道E3 / DS3 / STS - 1线路接口单元

特点

接收器

- 40 ° C至85°C工业级温度范围

发送接口特性

（可重构，

Relayless

R

3

技术

冗余）

输入抖动容限

接受来自任何单轨或双轨数据

终端设备，并产生一个双极性信号

到行

片上时钟和数据恢复电路高

会见E3 / DS3 / STS - 1抖动容限要求

检测并清除LOS按G.775

接收监控模式处理多达20分贝平

与6分贝电缆的衰减损耗

集成的脉冲整形电路

内置B3ZS / HDB3编码器（其可以是

禁用）

接受发送时钟为30％占空比 -

70%

芯片B3ZS / HDB3编码器和解码器，可

可以启用或禁用

生成符合ITU -T G.703脉冲

对于E3应用脉冲模板

片上时钟合成器提供适当的

从单一12.288 MHz的时钟速率时钟

生成符合DSX - 3脉冲的脉冲

模板，如在符合Bellcore GR -499中指定

-core

和ANSI T1.102_1993

提供低抖动输出时钟

发射机

生成符合STSX - 1脉冲

Relayless

脉冲模板，如在Bellcore的指定GR- 253-

CORE

R

3

技术

冗余）

（可重构，

发射机可以以支持被关闭

冗余设计

接收接口特性

符合符合Bellcore GR - 499 ， GR- 253和ANSI

T1.102规范发射脉冲

三态的冗余发送输出能力

应用

集成自适应接收均衡（可选）

最佳的时钟和数据恢复

每个发射器可以打开或关闭开启

传感器可提供电流输出驱动器

控制和诊断

声明并清除按照ITU-T的LOS缺陷

为E3和DS3应用G.775的要求

会见抖动容限要求，规定

在ITU -T G.823_1993的E3应用

控制并行微处理器接口和

CON组fi guration

会见抖动容限要求，规定

在符合Bellcore GR -499 -CORE的DS3应用

支持

监测

可选

国内

发送

司机

每个通道都支持模拟，远程和数字

环背

声明的锁（ LOL ）报警丢失

内置B3ZS / HDB3解码器（其可以是

禁用）

单3.3 V± 5 ％电源

5V电压的数字量输入

可提供420针TBGA耐热增强型

包

恢复的数据可以被静音，而LOS

条件声明

输出是单轨道或双轨道数据的

终端设备

2

XRT73R12

十二通道E3 / DS3 / STS - 1线路接口单元

初步

目录

REV 。 P1.0.3

一般DESCRIPTION.............................................................................................................. 1

A

PPLICATIONS

............................................................................................................................................................... 1

F

IGURE

1. B

LOCK

D

的作者IAGRAM

XRT 73R12 .................................................................................................................................... 1

订购信息.................................................................................................................... 1

F

EATURES

..................................................................................................................................................................... 2

T

RANSMIT

I

覆盖整个院落

C

极特

....................................................................................................................... 2

R

ECEIVE

I

覆盖整个院落

C

极特

......................................................................................................................... 2

引脚说明（按功能） ............................................ .............................................. 3

S

变体系

-S

IDE

T

RANSMIT

I

NPUT和

T

RANSMIT

C

ONTROL

P

插件

....................................................................................... 3

S

变体系

-S

IDE

R

ECEIVE

O

和安输出

R

ECEIVE

C

ONTROL

P

插件

....................................................................................... 6

R

ECEIVE

L

INE

S

IDE

P

插件

............................................................................................................................................... 8

C

LOCK

I

覆盖整个院落

......................................................................................................................................................... 9

G

ENERAL

C

ONTROL

P

插件

............................................................................................................................................ 10

P

OWER

S

UPPLY

P

插件

.................................................................................................................................................. 12

G

圆

P

插件

............................................................................................................................................................. 13

功能说明...................................................................................................... 18

1.0 R3技术（可重构， RELAYLESS冗余） ....................................... 18

1.1网络架构......................................................................................................................... 18

F

IGURE

2. N

ETWORK

R

EDUNDANCY

A

体系结构的设计

............................................................................................................................. 18

2.0时钟合成器....................................................................................................................... 19

2.1时钟分配................................................................................................................................. 19

F

IGURE

4. C

LOCK

D

ISTRIBUTION

C

ONGIFURED IN

E3 M

ODE

W

ITHOUT

U

星

SFM ................................................. ............................... 19

F

IGURE

3. S

IMPLIFIED

B

LOCK

D

的作者IAGRAM

I

NPUT

C

LOCK

C

IRCUITRY

D

分料的

M

ICROPROCESSOR

............................................ 19

3.0接收器部分.................................................................................................................. 20

F

IGURE

5. R

ECEIVE

P

ATH

B

LOCK

D

IAGRAM

.......................................................................................................................................... 20

3.1接收线路接口.......................................................................................................................... 20

F

IGURE

6. R

ECEIVE

L

INE

I

覆盖整个院落

C

ONNECTION

................................................................................................................................. 20

3.2自适应增益控制（AGC ） .............................................................................................................. 21

3.3接收均衡器................................................................................................................................... 21

F

IGURE

7. ACG / E

QUALIZER

B

LCOK

D

IAGRAM

....................................................................................................................................... 21

3.3.1建议FOR均衡器设置........................................... .................................................. 21

3.4时钟和数据恢复................................................................................................................... 21

3.4.1数据/时钟恢复模式............................................................................................................................ 21

3.4.2培训MODE........................................................................................................................................................ 21

3.5 LOS （信号丢失）检测仪........................................................................................................... 22

3.5.1 DS3 / STS - 1 LOS条件..................................................................................................................................... 22

3.5.2禁止ALOS / DLOS检测..................................................................................................................... 22

T

ABLE

2: T

HE

ALOS （A

NALOG

LOS ）D

ECLARATION和

C

LEARANCE

T

HRESHOLDS对于一个给定的地点

LOSTHR

和

REQEN （ DS3

和

STS - 1

PPLICATIONS

) .......................................................................................................................................................... 22

3.5.3 E3 LOS CONDITION:.................................................................................................................................................. 23

F

IGURE

8. L

OSS

O

F

S

IGNAL

D

EFINITION FOR

E3

按照

ITU -T G.775 ............................................ .................................................. .... 23

F

IGURE

9. L

开放源码软件

S

IGNAL

D

EFINITION FOR

E3

按照

ITU -T G.775................................................................................................... 23

3.5.4干扰TOLERANCE.................................................................................................................................. 24

F

IGURE

10. I

干涉现象

M

ARGIN

T

美东时间

S

ET UP FOR

DS3 / STS-1 ...................................................................................................... 24

F

IGURE

11. I

干涉现象

M

ARGIN

T

美东时间

S

ET UP FOR

E3. ................................................................................................................... 24

T

ABLE

3: I

干涉现象

M

ARGIN

T

美东时间

R

ESULTS

................................................................................................................................. 25

3.5.5静音带LOS情况恢复的数据： ....................................... ............................................ 26

3.6 B3ZS / HDB3解码器.................................................................................................................................. 26

F

IGURE

12. R

ECEIVER

D

ATA输出和违章时序

........................................................................................................ 26

4.0发射器部分........................................................................................................... 27

F

IGURE

13. T

RANSMIT

P

ATH

B

LOCK

D

IAGRAM

...................................................................................................................................... 27

4.1传输数字输入接口..................................................................................................... 27

F

IGURE

14. T

终端之间的设备和YPICAL界面

XRT73R12 （

双

-

RAIL数据

) .............................................. 27

F

IGURE

15. T

变送器

T

端子

I

NPUT

T

即时通信

............................................................................................................................... 28

F

IGURE

16. S

炉火

-R

AIL或

NRZ

ATA

F

ORMAT

(E

NCODER和

D

ECODER ARE

E

NABLED

) .................................................................. 28

4.2发送时钟........................................................................................................................................ 29

4.3 B3ZS / HDB3编码器.................................................................................................................................. 29

4.3.1 B3ZS编码....................................................................................................................................................... 29

4.3.2 HDB3 ENCODING....................................................................................................................................................... 29

I

XRT73R12

十二通道E3 / DS3 / STS - 1线路接口单元

REV 。 P1.0.3

初步

F

IGURE

17. D

UAL

-R

AIL

D

ATA

F

ORMAT

(

编码器和解码器将被禁用

).................................................................................... 29

F

IGURE

18. B3ZS ê

NCODING

F

ORMAT

................................................................................................................................................. 29

4.4 TRANSMIT脉冲整形.........................................................................................................................三十

F

IGURE

20. T

RANSMIT

P

ULSE

S

高原肺水肿

T

美东时间

C

IRCUIT

.............................................................................................................................. 30

4.4.1准则使用发送打造出电路........................................ .......................................... 30

F

IGURE

19. HDB3 ê

NCODING

F

ORMAT

................................................................................................................................................. 30

4.5 E3线路侧参数........................................................................................................................ 31

F

IGURE

21. P

ULSE

M

征求

E3 (34.368

兆位

/

S

)

接口符合ITU

-

T

G.703 ............................................................................. 31

T

ABLE

4 ： E3牛逼

变送器线路侧器输出和接收线路侧输入规范

.............................................................. 32

F

IGURE

22. B

ELLCORE

GR - 253心T

RANSMIT

O

安输出

P

ULSE

T

EMPLATE FOR

SONET STS - 1

PPLICATIONS

................................. 33

T

ABLE

5 ： STS -1 P

ULSE

M

ASK

E

QUATIONS

........................................................................................................................................... 33

T

ABLE

6 ： STS - 1 T＆

变送器

L

INE

S

IDE

O

和安输出

R

ECEIVER

L

INE

S

IDE

I

NPUT

S

PECIFICATIONS

（ GR- 253 ） ..................................... 34

F

IGURE

23. T

RANSMIT

O

UPUT

P

ULSE

T

EMPLATE FOR

DS3

按照

B

ELLCORE

GR- 499 ............................................... .......................... 34

T

ABLE

8 ： DS3牛逼

变送器

L

INE

S

IDE

O

和安输出

R

ECEIVER

L

INE

S

IDE

I

NPUT

S

PECIFICATIONS

（ GR- 499 ） ........................................ 35

T

ABLE

7 ： DS3 P

ULSE

M

ASK

E

QUATIONS

............................................................................................................................................... 35

4.6传递驱动MONITOR ........................................................................................................................ 36

4.7发射器部分的ON / OFF ............................................................................................................... 36

F

IGURE

24. T

RANSMIT

D

河

M

ONITOR SET

-

UP

................................................................................................................................... 36

5.0抖动..................................................................................................................................................37

5.1抖动容限..................................................................................................................................... 37

5.1.1 DS3 / STS - 1的抖动容限要求....................................... .................................................. ....... 37

F

IGURE

25. J

伊特尔

T

OLERANCE

M

EASUREMENTS

.................................................................................................................................. 37

5.1.2 E3抖动容限要求.............................................................................................................. 38

F

IGURE

26. I

NPUT

J

伊特尔

T

OLERANCE

F

OR

DS3 / STS-1 ...................................................................................................................... 38

F

IGURE

27. I

NPUT

J

伊特尔

T

OLERANCE FOR

E3..................................................................................................................................... 38

5.2抖动转移........................................................................................................................................ 39

T

ABLE

9: J

伊特尔

A

MPLITUDE VERSUS

M

ODULATION

F

Characteristic低频

(J

伊特尔

T

OLERANCE

) ........................................................................... 39

T

ABLE

10: J

伊特尔

T

转让（BOT）

S

PECIFICATION

/R

EFERENCES

................................................................................................................... 39

T

ABLE

11: J

伊特尔

T

转让（BOT）

P

屁股

M

ASKS

........................................................................................................................................... 39

5.2.1抖动GENERATION................................................................................................................................................ 40

F

IGURE

28. J

伊特尔

T

转让（BOT）

R

EQUIREMENTS

..................................................................................................................................... 40

6.0诊断功能...................................................................................................................41

6.1 PRBS发生器和检测......................................................................................................... 41

F

IGURE

29. PRBS模式................................................................................................................................................................... 41

6.2环回.................................................................................................................................................. 42

6.2.1模拟环回................................................................................................................................................ 42

F

IGURE

30. A

NALOG

L

OOPBACK

........................................................................................................................................................... 42

6.2.2数字环................................................................................................................................................. 43

6.2.3远方返回................................................................................................................................................ 43

F

IGURE

31. D

IGITAL

L

OOPBACK

............................................................................................................................................................ 43

F

IGURE

32. R

EMOTE

L

OOPBACK

........................................................................................................................................................... 43

6.3传输所有ONES （ TAOS ） ...................................................................................................................... 44

F

IGURE

33. T

RANSMIT

A

LL

O

NES

（ TAOS ） ............................................................................................................................................ 44

7.0微处理器接口模块.............................................. .......................................... 45

T

ABLE

12: S

选举

M

ICROPROCESSOR

I

覆盖整个院落

M

ODE

.......................................................................................................... 45

F

IGURE

34. S

IMPLIFIED

B

LOCK

D

的作者IAGRAM

M

ICROPROCESSOR

I

覆盖整个院落

B

LOCK

........................................................................ 45

7.1微处理器接口闭塞信号............................................ ............................. 46

T

ABLE

13 ： XRT73R12 M

ICROPROCESSOR

I

覆盖整个院落

S

IGNALS

............................................................................................................ 46

7.2异步和同步说明............................................. ............................. 47

T

ABLE

14: A

同步

T

即时通信

S

PECIFICATIONS

............................................................................................................................. 48

F

IGURE

35. A

同步

我μP

覆盖整个院落

S

IGNALS

D

URING

P

ROGRAMMED

I / O

EAD和

W

RITE

O

PERATIONS

.................................. 48

F

IGURE

36. S

YNCHRONOUS

我μP

覆盖整个院落

S

IGNALS

D

URING

P

ROGRAMMED

I / O

EAD和

W

RITE

O

PERATIONS

.................................... 49

T

ABLE

15: S

YNCHRONOUS

T

即时通信

S

PECIFICATIONS

............................................................................................................................... 49

7.3寄存器映射............................................................................................................................................. 50

T

ABLE

16:

C

OMMAND

R

EGISTER

A

地址H1

M

AP

,

WITHIN THE

XRT73R12 ................................................. ........................................... 50

全球/芯片级寄存器................................................................................................................ 59

寄存器描述 - 全局寄存器............................................. .................................................. 59

T

ABLE

17:

T

ABLE

18:

T

ABLE

19:

T

ABLE

20:

T

ABLE

21:

T

ABLE

22:

L

IST和

A

地址H1

L

作者OCATIONS

G

叶形

R

EGISTERS

........................................................................................................ 59

APS / R

EDUNDANCY

T

RANSMIT

C

ONTROL

R

EGISTER

- CR0 （A

地址H1

L

OCATION

= 0

X

00) ..................................................... 59

APS / R

EDUNDANCY

T

RANSMIT

C

ONTROL

R

EGISTER

- CR8 （A

地址H1

L

OCATION

= 0

X

08) ..................................................... 60

C

HANNEL

L

伊维尔基尼

I

NTERRUPT

E

NABLE

R

EGISTER

- CR96 （A

地址H1

L

OCATION

= 0

X

60) ......................................................... 61

C

HANNEL

L

伊维尔基尼

I

NTERRUPT

E

NABLE

R

EGISTER

- CR224 （A

地址H1

L

OCATION

= 0

X

E0)....................................................... 62

T

HE IS以上

: C

HANNEL

L

伊维尔基尼

I

NTERRUPT

S

TATUS

R

EGISTER

- CR97 （A

地址H1

L

OCATION

= 0

X

61) .................................. 63

II

XRT73R12

十二通道E3 / DS3 / STS - 1线路接口单元

初步

REV 。 P1.0.3

T

ABLE

23: C

HANNEL

L

伊维尔基尼

I

NTERRUPT

S

TATUS

R

EGISTER

- CR225 （A

地址H1

L

OCATION

= 0

X

E1)....................................................... 63

T

ABLE

24: D

EVICE

/P

艺术

N

棕土

R

EGISTER

- CR110 （A

地址H1

L

OCATION

= 0

X

6E) ........................................................................... 64

T

ABLE

25: C

HIP

R

EVISION

N

棕土

R

EGISTER

- CR111 （A

地址H1

L

OCATION

= 0

X

6F) ......................................................................... 64

每通道REGISTERS........................................................................................................................... 65

寄存器描述 - 每个通道寄存器............................................ ........................................ 66

T

ABLE

26:

T

ABLE

27:

T

ABLE

28:

T

ABLE

29:

T

ABLE

30:

T

ABLE

31:

T

ABLE

32:

T

ABLE

33:

T

ABLE

34:

T

ABLE

35:

T

ABLE

36:

T

ABLE

37:

T

ABLE

38:

T

ABLE

39:

T

ABLE

40:

T

ABLE

41:

T

ABLE

42:

T

ABLE

43:

XRT73R12

EGISTER

地图

展示

I

NTERRUPT

E

NABLE

R

EGISTERS

（ IER_

N

).................................................................. 66

S

环境允许

L

伊维尔基尼

I

NTERRUPT

E

NABLE

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

1 .................................................... 66

XRT73R12

EGISTER

地图

展示

I

NTERRUPT

S

TATUS

R

EGISTERS

（ ISR_

N

).................................................................. 68

S

环境允许

L

伊维尔基尼

I

NTERRUPT

S

TATUS

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

2 .................................................... 68

XRT73R12

EGISTER

地图

展示

A

LARM

S

TATUS

R

EGISTERS

（附上as_

N

) .......................................................................... 70

A

LARM

S

TATUS

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

3................................................................................... 70

XRT73R12

EGISTER

地图

展示

T

RANSMIT

C

ONTROL

R

EGISTERS

（ TC_

N

)................................................................... 73

T

RANSMIT

C

ONTROL

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

4 ........................................................................... 73

XRT73R12

EGISTER

地图

展示

R

ECEIVE

C

ONTROL

R

EGISTERS

（ RC_

N

) .................................................................... 75

R

ECEIVE

C

ONTROL

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

5 ............................................................................. 75

XRT73R12

EGISTER

地图

展示

C

HANNEL

C

ONTROL

R

EGISTERS

(CC_

N

) ................................................................... 76

C

HANNEL

C

ONTROL

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

6 ............................................................................ 76

XRT73R12

EGISTER

地图

展示

E

RROR

C

OUNTER

最高位

YTE

R

EGISTERS

（ EM_

N

)........................................................ 79

E

RROR

C

OUNTER

最高位

YTE

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

A................................................................. 79

XRT73R12

EGISTER

地图

展示

E

RROR

C

OUNTER

最低位

YTE

R

EGISTERS

（ EL_

N

).......................................................... 79

E

RROR

C

OUNTER

最低位

YTE

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

B.................................................................. 80

XRT73R12

EGISTER

地图

展示

E

RROR

C

OUNTER

H

掩门

R

EGISTERS

（ EH_

N

) ........................................................ 80

E

RROR

C

OUNTER

H

掩门

R

EGISTER

- C

HANNEL

A

地址H1

L

OCATION

= 0

XM

C ................................................................ 81

8.0电气特性............................................... .................................................. .. 82

T

ABLE

44: A

BSOLUTE

M

AXIMUM

R

ATINGS

............................................................................................................................................. 82

T

ABLE

45 ： DC é

LECTRICAL

C

极特

:..................................................................................................................................... 82

订购信息.................................................................................................................. 83

P

ACKAGE

D

IMENSIONS

- .............................................................................................................................................. 83

R

EVISIONS

.................................................................................................................................................................. 84

III