【DS2155T1 / E1 / J1单芯片收发器www.maxim-ic.com概述该DS2155是】,IC型号DS21352,DS21352 PDF资料,DS21352经销商,ic,电子元器件-51电子网

DS2155

T1 / E1 / J1单芯片收发器

www.maxim-ic.com

概述

该DS2155是一个软件可选的T1 ，E1或J1

单芯片收发器（ SCT ）短途和

长途应用。该DS2155是由

一个线路接口单元（LIU ），成帧器， HDLC控制器

和一个TDM背板接口，并且通过控制

配置为Intel或Motorola的8位并行口

公交车运营。该DS2155是引脚和软件

与DS2156兼容。

刘是由发射和接收

接口和抖动衰减器。发送

接口负责生成必要

波形，用于驱动该网络，并提供

根据不同的类型选择正确的源阻抗

媒体使用。 T1波形生成包括

DSX -1线路附加件和CSU线路外附

的-7.5dB ， -15dB和-22.5db，可E1波形

代包括G.703波形为75Ω

同轴线或120Ω双绞线电缆。该接收接口

提供网络终端和恢复时钟和

来自网络的数据。

特点

完整的T1 / DS1 / ISDN - PRI / J1收发器

的功能

完整的E1 （CEPT ）的PCM -30 / ISDN-PRI

收发器功能

长途和短途线路接口

时钟/数据恢复和波形整形

CMI编码器/解码器，光学I / F

晶振的抖动衰减器

完全独立的发送和接收

的功能

双HDLC控制器

可编程BERT发生器与检测器

内部软件可选接收和

发送方的终端电阻

75Ω / 100Ω / 120Ω T1和E1接口

双帧弹性缓存滑动缓冲器，

连接到异步背板最多

16.384MHz

16.384MHz的， 8.192MHz的， 4.096MHz或

2.048MHz的时钟输出到合成

恢复网络时钟

应用

T1 / E1 / J1线卡

交换机和路由器

分插复用器

产品特点继续

第2页。

订购信息

部分

DS2155L

DS2155LN

DS2155G

DS2155GN

温度范围

0 ° C至+ 70°C

-40 ° C至+ 85°C

0 ° C至+ 70°C

-40 ° C至+ 85°C

PIN- PACKAGE

100 LQFP

10毫米CSBGA

T1/E1/J1

网

DS2155

T1/E1/J1

SCT

背板

TDM

注意：

该器件的一些修订可能偏离称为勘误表公布的规格。任何器件的多个版本

可能同时获得通过不同的销售渠道。欲了解器件勘误表的信息，请点击这里： www.maxim-ic.com/errata 。

1 240

100903

DS2155

1.目录

桌子， CONTENTS..................................................................................................................................2

1.1

1.2

干练

IGURES

........................................................................................................................................6

干练

ABLES

..........................................................................................................................................7

数据手册版本历史...........................................................................................................8

主要特点.........................................................................................................................................10

3.1

3.2

UNCTIONAL

ESCRIPTION

.........................................................................................................................13

LOCK

IAGRAM

.........................................................................................................................................15

RANSMIT

IDE

...........................................................................................................................................19

ECEIVE

IDE

..............................................................................................................................................22

ARALLEL

ONTROL

ORT

插件

.................................................................................................................26

XTENDED

变体系

载文信息

......................................................................................................27

SER

安输出

ORT

插件

............................................................................................................................28

JTAG牛逼

美东时间

CCESS

ORT

插件

...................................................................................................................29

INE

覆盖整个院落

插件

..................................................................................................................................30

UPPLY

插件

................................................................................................................................................31

和

克对

ACKAGE

INOUT

.........................................................................................................................32

CSBGA P

ONFIGURATION

......................................................................................................34

EGISTER

............................................................................................................................................35

引脚功能说明.................................................................................................................19

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

并行端口.........................................................................................................................................35

5.1

规划模型..........................................................................................................................41

6.1 P

OWER

-U

EQUENCE

.................................................................................................................................42

6.1.1

主模式Register.........................................................................................................................42

6.2 I

NTERRUPT

ANDLING

................................................................................................................................43

6.3 S

TATUS

EGISTERS

......................................................................................................................................43

6.4 I

载文信息

EGISTERS

...........................................................................................................................44

6.5 I

NTERRUPT

载文信息

EGISTERS

........................................................................................................44

特殊每通道寄存器操作............................................ ................................. 45

CLOCK地图..................................................................................................................................................47

T1成帧器/ FORMATTER控制和状态寄存器.......................................... ........ 48

9.1

9.2

9.3

9.4

ONTROL

EGISTERS

.............................................................................................................................48

T1 T

RANSMIT

RANSPARENCY

...................................................................................................................53

AIS- CI

和

RAI -CI摹

生成及

ETECTION

..................................................................................53

ECEIVE

-S

IDE

IGITAL

-M

ILLIWATT

ODE

eneration

.....................................................................54

E1成帧器/ FORMATTER控制和状态寄存器.......................................... ..57

ONTROL

EGISTERS

.........................................................................................................................57

UTOMATIC

LARM

eneration

.........................................................................................................61

我E1

载文信息

EGISTERS

.................................................................................................................62

通用控制和状态寄存器............................................. ............................. 64

T1 / E1 S

TATUS

EGISTERS

......................................................................................................................65

2 240

10.

10.1

10.2

10.3

11.

11.1

DS2155

12.

13.

13.1

14.

I / O引脚配置OPTIONS.................................................................................................71

环回配置..........................................................................................................73

-C

HANNEL

OOPBACK

......................................................................................................................75

错误计数寄存器...............................................................................................................77

14.1

INE

-C

ODE

IOLATION

'mount

EGISTER

(LCVCR).............................................................................78

14.1.1 T1 Operation.......................................................................................................................................78

14.1.2 E1 Operation.......................................................................................................................................78

14.2

ATH

ODE

IOLATION

'mount

EGISTER

（ PCVCR ） .............................. ............................. 80

14.2.1 T1 Operation.......................................................................................................................................80

14.2.2 E1 Operation.......................................................................................................................................80

14.3

RAMES

-S

YNC

'mount

EGISTER

(FOSCR)..............................................................................81

14.3.1 T1 Operation.......................................................................................................................................81

14.3.2 E1 Operation.......................................................................................................................................81

14.4

E- B

OUNTER

(EBCR).........................................................................................................................82

15.

16.

DS0监控功能...........................................................................................................83

信令操作.....................................................................................................................85

16.1

ECEIVE

ignaling

...............................................................................................................................85

基于处理器16.1.1 Signaling.................................................................................................................85

16.1.2基于硬件的接收信号...................................................................................................86

16.2

RANSMIT

ignaling

.............................................................................................................................91

16.2.1处理器的模式.......................................................................................................................91

16.2.2软件信号插入使能寄存器， E1 CAS模式..................................... ..................... 95

16.2.3软件信号插入使能寄存器， T1模式...................................... ............................ 97

基于硬件16.2.4 Mode.......................................................................................................................97

17.

17.1

18.

19.

每信道空闲码生成............................................ ........................................ 98

DLE

-C

ODE

AGC软件

XAMPLES

..................................................................................................99

通道阻滞寄存器............................................... ................................................. 103

弹性存储器OPERATION........................................................................................................106

19.1

ECEIVE

IDE

........................................................................................................................................109

19.1.1 T1模式............................................................................................................................................109

19.1.2 E1 Mode............................................................................................................................................109

19.2

RANSMIT

IDE

.....................................................................................................................................109

19.2.1 T1模式............................................................................................................................................110

19.2.2 E1 Mode............................................................................................................................................110

19.3

LASTIC

TORES

NITIALIZATION

.........................................................................................................110

19.4

最小值：

ELAY

ODE

.......................................................................................................................110

20.

21.

G.706中级CRC- 4更新（ E1模式） ..................................... .............. 111

T1面向位的代码（ BOC ）控制器......................................... ................................. 112

21.1

RANSMIT

BOC.....................................................................................................................................112

发送BOC ..............................................................................................................................................112

21.2

ECEIVE

中国银行.......................................................................................................................................112

收到中国银行................................................................................................................................................112

22.

附加（ SA ）和国际（ SI ）位操作（仅限于E1 ） ...................... 115

3的240

DS2155

22.1

22.2

22.3

23.

ETHOD

1: H

ARDWARE

CHEME

.........................................................................................................115

ETHOD

2: I

NTERNAL

EGISTER

CHEME

ASED ON

OUBLE

-F

RAME

..............................................115

ETHOD

3: I

NTERNAL

EGISTER

CHEME

ASED ON

CRC4 M

ULTIFRAME

........................................118

HDLC控制器........................................................................................................................128

23.1

ASIC

PERATION

ETAILS

..................................................................................................................128

23.2

HDLC

ONFIGURATION

........................................................................................................................128

23.2.1 FIFO Control....................................................................................................................................132

23.3

HDLC M

APPING

....................................................................................................................................133

23.3.1 Receive..............................................................................................................................................133

23.3.2发送............................................................................................................................................135

23.3.3 FIFO信息.............................................................................................................................140

23.3.4接收数据包字节Available........................................................................................................140

23.3.5 HDLC的FIFO ....................................................................................................................................141

23.4

ECEIVE

HDLC

ODE

XAMPLE

..........................................................................................................142

23.5

EGACY

FDL S

UPPORT

（ T1 M

ODE

)......................................................................................................142

23.5.1概述...........................................................................................................................................142

23.5.2接收部分.................................................................................................................................142

23.5.3发送部分...............................................................................................................................144

23.6

D4 / SLC -96

PERATION

........................................................................................................................144

24.

线路接口单元（ LIU） ...........................................................................................................145

24.1

刘

PERATION

....................................................................................................................................145

24.2

ECEIVER

..............................................................................................................................................145

24.2.1接收电平指示器和阈值中断......................................... .................................... 146

24.2.2接收G.703同步信号（ E1模式） ..................................... ...................................... 146

24.2.3监控模式...................................................................................................................................146

24.3

变送器

.......................................................................................................................................147

24.3.1发送短路Detector/Limiter..........................................................................................147

24.3.2发送开路Detector.......................................................................................................147

24.3.3发送BPV错误插入..........................................................................................................147

24.3.4发送G.703同步信号（ E1模式） ..................................... .................................... 147

24.4

MCLK P

重新依比例调整

...............................................................................................................................148

24.5

伊特尔

TTENUATOR

.............................................................................................................................148

24.6

CMI （C

ODE

ARK

n版本

) O

PTION

...............................................................................................148

24.7

刘成

ONTROL

EGISTERS

....................................................................................................................149

24.8

ECOMMENDED

IRCUITS

.....................................................................................................................158

24.9

OMPONENT

PECIFICATIONS

...............................................................................................................160

25.

26.

26.1

26.2

26.3

26.4

26.5

26.6

27.

可编程带内循环代码生成和检测...................... 165

BERT FUNCTION..................................................................................................................................172

TATUS

..................................................................................................................................................172

APPING

...............................................................................................................................................172

BERT

EGISTER

ESCRIPTIONS

...........................................................................................................174

BERT

EPETITIVE

ATTERN

..........................................................................................................178

BERT B

OUNTER

.............................................................................................................................179

BERT ê

RROR

OUNTER

.......................................................................................................................180

有效载荷ERROR -插入函数（ T1模式） ........................................ ........ 182

27.1

棕土

-E

RRORS

EGISTERS

..........................................................................................................184

27.1.1数-的，左的错误Register........................................................................................................185

28.

交错PCM总线操作（ IBO ） ........................................... .................................... 186

4 240

DS2155

28.1

28.2

29.

30.

31.

32.

33.

34.

34.1

34.2

34.3

34.4

34.5

34.6

35.

35.1

35.2

36.

37.

37.1

37.2

37.3

37.4

37.5

38.

38.1

38.2

HANNEL

NTERLEAVE

.........................................................................................................................186

RAME

NTERLEAVE

..............................................................................................................................186

扩展系统信息总线（ ESIB ） ........................................... ............................ 189

可编程背板时钟合成器.............................................. .......... 193

部分T1 / E1支持.........................................................................................................193

用户可编程输出引脚上............................................. ........................................... 195

发送流CHARTS...............................................................................................................196

JTAG边界扫描结构和测试访问端口................................. 201

ESCRIPTION

.........................................................................................................................................201

NSTRUCTION

EGISTER

........................................................................................................................204

美东时间

EGISTERS

....................................................................................................................................206

OUNDARY

可以

EGISTER

.................................................................................................................206

YPASS

EGISTER

.................................................................................................................................206

DENTIFICATION

EGISTER

...................................................................................................................206

功能时序DIAGRAMS.................................................................................................210

T1 M

ODE

...............................................................................................................................................210

E1 M

ODE

...............................................................................................................................................215

操作参数..............................................................................................................224

AC时序参数和图表............................................. .................................. 226

ULTIPLEXED

AC - C

极特

..........................................................................................226

ONMULTIPLEXED

AC - C

极特

...................................................................................229

ECEIVE

-S

IDE

AC - C

极特

..................................................................................................232

无源底板

LOCK

即时通信

： AC - C

极特

.........................................................................235

RANSMIT

AC - C

极特

........................................................................................................236

力学描述..........................................................................................................239

LQFP （ L） P

ACKAGE

.............................................................................................................................239

CSBGA （ G） P

ACKAGE

..........................................................................................................................240

5 240

DS21352 3.3V和5V DS21552

T1单芯片收发器

www.maxim-ic.com

特点

完整的DS1 / ISDN - PRI / J1收发器功能

长途和短途刘

晶体抖动衰减器

编译生成超时DSX - 1和CSU线路

HDLC控制器，带有64字节缓冲器，可配置为

FDL或DS0操作

双帧弹性缓存滑动缓冲器，可以

连接到异步背板高达8.192MHz的

8.192MHz的时钟输出锁定到RCLK

交错式PCM总线操作

每通道环回和空闲代码插入

8位并行控制端口复用功能或nonmuxed巴士

（ Intel或Motorola ）

可编程输出时钟的部分T1

完全独立的发送和接收功能

产生/检测带内循环代码从1到8位

在长度，包括CSU环路码

IEEE 1149.1 JTAG边界扫描

引脚与DS2152 / 54 / 554分之354 SCT的兼容

100引脚LQFP封装（14毫米× 14毫米） 3.3V

（ DS21352 ）或5V （ DS21552 ）供应;低功耗

CMOS

引脚分配

DS21352

DS21552

100

订购信息

DS21352L

DS21352LN

DS21552L

DS21552LN

（ 0 ° C至+ 70 ° C）

（ -40 ° C至+ 85°C ）

（ 0 ° C至+ 70 ° C）

（ -40 ° C至+ 85°C ）

描述

该DS21352 / 552 T1单芯片收发器包含了所有必要的功能，用于连接T1

线无论是DS1长途或DSX - 1短程。时钟恢复电路将自动

调整到T1线路从0英尺到6000英尺的长度。该设备可以生成DSX - 1行生成

奏和CSU线路奏-7.5dB ， -15dB和-22.5dB的。内建的抖动衰减器

（选择为32位或128位）可以被放置在任何发送或接收数据的路径。该

成帧器定位帧和复帧边界，并监视警报的数据流。它也是

用于提取和插入夺位信令数据和FDL数据。该器件包含了一组

内部寄存器，用户可以访问和控制单元的操作。通过快速访问

并行控制端口允许一个单一的控制器来处理多条T1线路。该器件完全满足所有的

最新的T1规格，包括ANSI T1.403-1995 ， ANSI T1.231-1993 ， AT&T TR 62411 （ 12-90 ）

AT&T TR54016和ITU G.703 ， G.704 ， G.706 ， G.823和I.431 。

1 137

120501

DS21352/DS21552

图目录.........................................................................................................................5

表格清单...........................................................................................................................6

INTRODUCTION............................................................................................................................7

3.1功能DESCRIPTION..............................................................................................8

3.2文档版本历史.............................................. ...................................... 10

引脚说明......................................................................................................................11

4.1引脚功能DESCRIPTION..........................................................................................17

4.1.1发送端引脚........................................................................................................17

4.1.2接收端引脚..........................................................................................................20

4.1.3并行控制端口引脚........................................... ................................................. 23

4.1.4 JTAG测试访问端口引脚.......................................... ............................................... 25

4.1.5交织总线操作销........................................... ........................................... 25

4.1.6线接口引脚........................................................................................................26

4.1.7供应Pins....................................................................................................................27

并行PORT........................................................................................................................28

5.1寄存器映射...................................................................................................................28

控制，ID和测试寄存器........................................... ...................................... 32

6.1 POWER- UP SEQUENCE......................................................................................................32

6.2器件ID ............................................................................................................................32

6.3有效载荷LOOPBACK.......................................................................................................37

6.4 FRAMER LOOPBACK .........................................................................................................38

6.5脉冲密度ENFORCER .............................................. .............................................. 40

6.6远方返回.........................................................................................................44

状态和信息寄存器.............................................. ............................ 45

错误计数寄存器....................................................................................................52

8.1线路编码违例计数寄存器（ LCVCR ） ......................................... ....... 53

8.2路径编码违例计数寄存器（ PCVCR ） ......................................... ...... 54

8.3多帧不同步计数寄存器（ MOSCR ） .................................... 55

DSO监测FUNCTION...............................................................................................56

2 137

DS21352/DS21552

10.

11.

12.

13.

14.

15.

信令OPERATION..........................................................................................................58

10.1处理器的信令............................................. ....................................... 58

10.2 HARDWARD的信令............................................. ...................................... 60

10.2.1接收Side.................................................................................................................60

10.2.2发送Side...............................................................................................................61

每信道编码（ IDLE ）的生成.......................................... ............................ 61

11.1发送端代码生成............................................. .............................. 62

11.1.1修正了每信道空闲代码插入........................................ .............................. 62

11.1.2独特的每通道空闲码插入........................................ ............................ 63

11.2接收端代码生成............................................. .................................. 63

11.2.1修正了每信道空闲代码插入........................................ .............................. 64

11.2.3独特的每通道空闲码插入........................................ ............................ 64

每通道LOOPBACK.....................................................................................................65

计数停止寄存器............................................... ............................................. 65

弹性存储器操作............................................... ............................................... 66

14.1接收端.....................................................................................................................66

14.2 TRANSMIT SIDE..................................................................................................................67

14.3弹性存储器初始化.............................................. .................................. 67

14.4最小延迟MODE..................................................................................................67

HDLC CONTROLLER.................................................................................................................68

15.1 HDLC FOR个DSO ..................................................................................................................68

15.1.1接收HDLC消息........................................... .............................................. 68

15.1.2传输的HDLC消息........................................... ............................................ 68

15.2 FDL / Fs的提取和插入........................................... .............................. 69

15.3 HDLC和BOC控制器的FDL .......................................... ...................... 69

15.3.1一般Overview........................................................................................................69

15.3.2状态寄存器的HDLC .......................................... ............................................ 70

15.3.3基本操作细节............................................ .................................................. 71

15.3.4 HDLC /银寄存器说明.......................................... ..................................... 72

15.4 LEGACY FDL SUPPORT.....................................................................................................82

15.4.1 Overview......................................................................................................................82

15.4.2接收部分............................................................................................................82

15.4.3发送部分..........................................................................................................84

15.5 D4 / SLC -96 OPERATION......................................................................................................84

3的137

DS21352/DS21552

16.

17.

18.

19.

20.

21.

22.

23.

24.

25.

LINE接口功能............................................... .................................................. 85

16.1接收时钟和数据恢复............................................ ........................ 85

16.2 TRANSMIT WAVE整形和线驱动........................................... ............ 86

16.3抖动ATTNUATOR..........................................................................................................86

16.4受保护INTERFACES................................................................................................92

16.5接收MONITOR MODE...............................................................................................95

可编程带内循环代码生成和检测............ 96

TRANSMIT透明度................................................ .................................................. 99

JTAG边界扫描结构和测试访问端口....................... 99

19.1说明......................................................................................................................99

19.2 TAP控制器状态机............................................. ............................. 101

19.3指令寄存器............................................... ................................................ 103

19.4测试寄存器..............................................................................................................105

交错PCM总线操作.............................................. ................................ 109

20.1通道交错............................................... .................................................. 111

20.2帧INTERLEAVE.......................................................................................................111

功能时序图............................................... ...................................... 111

接收和发送数据流图............................................ ......... 123

操作PARAMETERS...................................................................................................125

AC时序参数和图表............................................. ....................... 126

24.1复用总线交流特性............................................. ................ 126

24.2非复用总线交流特性........................................... ........ 129

24.3接收端交流特性............................................. .......................... 132

24.4 TRANSMIT交流特性.............................................. ................................ 136

机械DESCRIPTTION ................................................ ............................................ 139

4 137

DS21352/DS21552

1.图目录

图3-1 SCT BLOCK DIAGRAM.........................................................................................................9

图16-1外部模拟连接........................................... ............................... 87

图16-2可选晶振连接........................................... ............................... 88

图16-3发送波形TEMPLANE ........................................... ................................. 89

图16-4抖动容限.........................................................................................................91

图16-5抖动衰减....................................................................................................91

图16-6保护的接口实例为DS21552 ........................................ ... 93

图16-7保护的接口区为例TE DS21352 ........................................ ...... 94

图16-8普通监视器端口应用.......................................... .......................... 95

图19-1 JTAG功能框图.......................................... ............................ 100

图19-2 TAP控制器状态图.......................................... .............................. 103

图20-1 IBO的基本配置使用4 SCTS ........................................ .................... 110

图21-1接收端D4 TIMING.............................................................................................111

图21-2接收端ESF时序.......................................... ................................................. 112

图21-3接收端边界时序（禁用弹性店） .............................. 113

图21-4接收端1.544 MHz的边界时序（有弹力商店启用） ........... 113

图21-5接收端2.048 MHz的边界时序（有弹力商店启用） ........... 114

图21-6接收端交叉总线操作，字节模式.............................. 115

图21-7接收端交叉总线操作，帧模式........................... 116

图21-8发送端D4时序.......................................... ............................................... 117

图21-9发送端ESF时序.......................................... ............................................. 118

图21-10发送端边界时序（有弹力商店禁用） ........................ 119

图21-11发送端1.544 MHz的边界时序（有弹力商店启用） ...... 119

图21-12发送端2.048 MHz的边界时序（有弹力商店启用） ...... 120

图21-13发送端交错的总线操作，字节模式......................... 121

图21-14发送端交错的总线操作，帧模式..................... 122

图22-1接收数据流...................................................................................................123

图22-2传输数据FLOW................................................................................................124

图24-1 INTEL总线读时序（ BTS = 0 / MUX = 1 ） ................................. ............................ 127

图24-2 INTEL总线写入时序（ BTS = 0 / MUX = 1 ） ................................. .......................... 127

图24-3 Motorola总线时序（ BTS = 1 / MUX = 1 ） ................................. ............................ 128

图24-4 INTEL总线读时序（ BTS = 0 / MUX = 0 ） ................................. ............................. 130

图24-5 INTEL总线读时序（ BTS = 0 / MUX = 0 ） ................................. ............................ 130

图24-6 Motorola总线读时序（ BTS = 1 / MUX = 0 ） ................................. ................. 131

图24-7 Motorola总线读时序（ BTS = 1 / MUX = 0 ） ................................. ................. 131

图24-8接收端时序..................................................................................................133

图24-9接收端时序，弹性缓存使能....................................... ........ 134

图24-10接收线路接口时序.......................................... ............................... 135

图24-11发送端TIMING.............................................................................................137

图24-12发送端时序，弹性缓存使能....................................... ..138

图24-13发送线接口时序.......................................... ............................ 138

5 137

DS21352 3.3V和5V DS21552

T1单芯片收发器

www.maxim-ic.com

特点

完整的DS1 / ISDN - PRI / J1收发器功能

长途和短途刘

晶体抖动衰减器

编译生成超时DSX - 1和CSU线路

HDLC控制器，带有64字节缓冲器，可配置为

FDL或DS0操作

双帧弹性缓存滑动缓冲器，可以

连接到异步背板高达8.192MHz的

8.192MHz的时钟输出锁定到RCLK

交错式PCM总线操作

每通道环回和空闲代码插入

8位并行控制端口复用功能或nonmuxed巴士

（ Intel或Motorola ）

可编程输出时钟的部分T1

完全独立的发送和接收功能

产生/检测带内循环代码从1到8位

在长度，包括CSU环路码

IEEE 1149.1 JTAG边界扫描

引脚与DS2152 / 54 / 554分之354 SCT的兼容

100引脚LQFP封装（14毫米× 14毫米） 3.3V

（ DS21352 ）或5V （ DS21552 ）供应;低功耗

CMOS

引脚分配

DS21352

DS21552

100

订购信息

DS21352L

DS21352LN

DS21552L

DS21552LN

（ 0 ° C至+ 70 ° C）

（ -40 ° C至+ 85°C ）

（ 0 ° C至+ 70 ° C）

（ -40 ° C至+ 85°C ）

描述

该DS21352 / 552 T1单芯片收发器包含了所有必要的功能，用于连接T1

线无论是DS1长途或DSX - 1短程。时钟恢复电路将自动

调整到T1线路从0英尺到6000英尺的长度。该设备可以生成DSX - 1行生成

奏和CSU线路奏-7.5dB ， -15dB和-22.5dB的。内建的抖动衰减器

（选择为32位或128位）可以被放置在任何发送或接收数据的路径。该

成帧器定位帧和复帧边界，并监视警报的数据流。它也是

用于提取和插入夺位信令数据和FDL数据。该器件包含了一组

内部寄存器，用户可以访问和控制单元的操作。通过快速访问

并行控制端口允许一个单一的控制器来处理多条T1线路。该器件完全满足所有的

最新的T1规格，包括ANSI T1.403-1995 ， ANSI T1.231-1993 ， AT&T TR 62411 （ 12-90 ）

AT&T TR54016和ITU G.703 ， G.704 ， G.706 ， G.823和I.431 。

1 137

120501