CS4923/4/5/6/7/8/9
6.4 I
2
串行主机接口.............................................. .................................................. .. 39
6.4.1
I
2
C写的......................................................................................................... 39
6.4.2
I
2
C读取......................................................................................................... 39
6.5外部存储器.............................................................................................................. 41
6.5.1
外部存储器和自动引导.............................................. ........................ 43
数字输入&输出.............................................. .................................................. .. 44
7.1数字音频格式....................................................................................................... 44
7.2数字音频输入接口............................................. .................................................. ..... 46
7.3压缩后的数据输入端口............................................. .............................................. 46
7.4并行数字音频数据输入............................................ .......................................... 46
7.5数字音频输出端口............................................. .................................................. .. 47
7.5.1
IEC60958输出................................................ ............................................ 48
引脚说明.............................................................................................................. 49
包装尺寸...................................................................................................... 54
7.
8.
9.
图列表
图1 。
RESET
定时..................................................................................................................五
图2.串行压缩数据定时........................................... ............................................ 6
图3. CLKIN与CLKSEL = VSS = PLL使能....................................... ................................. 7
图4. CLKIN与CLKSEL = VD = PLL旁路....................................... .................................. 7
图5.英特尔并行主机模式读取周期......................................... ........................................ 9
图6.英特尔并行主模式写周期......................................... ........................................ 9
图7.摩托罗拉并行主机模式读取周期......................................... .............................. 11
图8.摩托罗拉并行主模式写周期......................................... ............................... 11
图9. SPI控制端口Timing................................................................................................... 13
图10.我
2
C控制端口时序.............................................. .................................................. 15
图11.数字音频输入，数据和时钟时序....................................... ............................ 17
图12.数字音频输出，数据和时钟时序....................................... ......................... 19
图13.我
2
Control..................................................................................................................... 25
图14.我
2
C控制与外部存储器............................................. .................................... 26
图15. SPI控制.................................................................................................................... 27
图16. SPI控制与外部存储器.......................................... ...................................... 28
图17.英特尔Parallel控制模式........................................... ................................................. 29
图18.摩托罗拉并联控制方式........................................... .......................................... 30
图19. SPI Timing..................................................................................................................... 38
图20.我
2
C定时等..................................................................................................................... 40
图21.外部存储器接口............................................ ................................................ 42
图22.运行时内存访问.......................................... .................................................. 42
图23.自动引导时机Diagram.............................................................................................. 43
图24.我
2
S格式..................................................................................................................... 45
图25.左对齐Format...................................................................................................... 45
图26.右Justified................................................................................................................ 45
图27.多通道格式（M == 20） ..................................... .............................................. 45
表格清单
表1.硅修订.............................................................................................................. 20
表2.主机模式...................................................................................................................... 33
表3.主机存储器映射............................................................................................................ 34
表4.英特尔并行主模式引脚分配......................................... ............................... 34
表5.并行输入/输出寄存器.......................................... ............................................... 35
表6.摩托罗拉并行主模式引脚分配......................................... ....................... 36
表7. SPI串行模式引脚分配.......................................... .......................................... 36
表8.我
2
串行模式引脚分配............................................. ....................................... 39
表9.内存接口Pins...................................................................................................... 41
表10.数字音频输入Port................................................................................................... 46
表11.压缩的数据输入端口........................................... ............................................... 46
表12.数字音频输出端口........................................... .................................................. ... 47
表13. MCLK / SCLK主模式比率......................................... ......................................... 47
DS262F2
3
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