引言
在为一个新设计的电信系统开发软件时，最棘手的任务莫过于实现基本的设备操作。ds26303收发器的大量功能和多端口操作使软件开发更趋复杂。 为了方便初期系统开发，dallas semiconductor公司提供了c风格范例代码，它可以在t1或e1模式下初始化设备，软件开发人员只需针对所需的操作修改代码，或编写与特定系统相关的功能。一旦代码编译完毕，即可载入系统进行测试与评估。需要注意的是ds26303有两个版本，分别是ds26303-120和ds26303-75。它们的区别很小，只会影响到几个设置，因此需要弄清楚设计中用到的是哪个器件。

代码范例

图1中所示的范例代码在稍加修改之后就可以正确编译以供目标系统使用。'write(address,data)'和'wait(milliseconds)'两个函数调用过程与系统相关，因此需要根据所用的微处理器编写。该代码假定设备被映射到16位的本地总线(地址偏移0x0000)，并且设备的数据总线为8位。 对于其他情况，则需要修改代码或编写函数调用来解决。此段代码还包含某些寄存器的多种不同设置，从而为开发人员提供了时钟频率、线路编码等参数的多种选择。虽然包含了大量的基本功能，但该代码并不完备。当需要实现其他附加功能时，请参考数据资料。

/*
configuration example for ds26303-120 running in e1 mode.

this example assumes e1 operation so the function call for t1/j1 configuration
has been commented out. simply comment out the e1 configuration function
call and uncomment the t1 configuration function call for t1 operation. an
individual function call for j1 operation is not present because it is very
similar to t1 operation and could easily be implemented in that function.

this file follows c style conventions. however actual code for the function
calls listed below are implementation specific and need to be added:

function calls: write(address, data), wait(milliseconds)


the following comments only indicate some of the possible clock sources
that can be used for either e1 or t1/j1 operation.

master clock configuration can use multiples of n = 1, 2, 4, or 8
mclk = can be a n x 1.544 or n x 2.048 mhz signal for e1 or t1/j1 operation

tclk = must be a 2.048 mhz signal for e1 operation
tclk = must be a 1.544 mhz signal for t1/j1 operation
*/

void initialization_main()
{
/* global initialization begin */

/* reset all channels to their default values */
write(0x001f, 0x00); // addp, set address pointer to primary register bank
write(0x000a, 0xff); // swr, reset all channels

/* wait 1 ms for reset to complete */
wait (1);

/* the master clock select register is important for proper */
/* device operation consult the data sheet for all possible configurations. */
write(0x001f, 0x01); // addp, set address pointer to individual liu register bank
write(0x0006, 0x00); // mc, e1 mode only mclk-2.048, teclk & clka disabled
// write(0x0006, 0x00); // mc, t1/j1 mode only mclk-1.544, teclk & clka disabled

// write(0x0006, 0x03); // mc, t1/j1 or e1 mode mclk-1.544, teclk & clka disabled
// write(0x0006, 0x07); // mc, t1/j1 or e1 mode mclk-3.088, teclk & clka disabled
// write(0x0006, 0x0b); // mc, t1/j1 or e1 mode mclk-6.176, teclk & clka disabled
// write(0x0006, 0x0f); // mc, t1/j1 or e1 mode mclk-12.352, teclk & clka disabled

// write(0x0006, 0x01); // mc, t1/j1 or e1 mode mclk-2.048, teclk & clka disabled
// write(0x0006, 0x05); // mc, t1/j1 or e1 mode mclk-4.096, teclk & clka disabled
// write(0x0006, 0x09); // mc, t1/j1 or e1 mode mclk-8.192, teclk & clka disabled
// write(0x0006, 0x0d); // mc, t1/j1 or e1 mode mclk-16.384, teclk & clka disabled

/* wait 1 ms for clock to settle after configuration */
wait (1);

/* the gc register is able to globally control the ais during los, short circuit */
/* protection, line coding, ja depth, ja position, and ja enable functions */
write(0x001f, 0x00); // addp, set address pointer to primary register bank
write(0x000f, 0x80); // gc, enable rx internal impedance, disable global controls

/* global