如何设计一个双时钟的计数器，其中一个时钟是clk_up另一个是clk_down？

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dou is
port ( clk1 : in std_logic;
clk2 : in std_logic;
q : out std_logic_vector(0 to 3)
);
end dou;
architecture rtl of dou is
signal q1,q2 : integer:=0;
begin
process(clk1)
begin
if clk1'event and clk1='1' then
q1<=q1+1;
end if;
end process;
process(clk2)
begin
if clk2'event and clk2='1' then
q2<=q2+1;
end if;
end process;
process(q1,q2)
begin
q<=conv_std_logic_vector(q1+q2,4);
end process;
end rtl;
==============================
neither maxplus nor any other rtl synthesis tool that the doctor is
familar with can cope with processes that are sensitive to more than one
clock, or more than one clock edge.

you must recast your model into multiple processes if you wish to
synthesize it.


-- demolbl

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