AM79Q021JC全新原装现货库存，联系电话：13590238352黄小姐（微信同号）
CONNECTION DIAGRAM (TQFP PACKAGE)
Top View
Notes:
1. Pin 1 is marked for orientation.
2. RSVD = Reserved pin; should not be connected externally to any signal or supply.
VCCD
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
26
25
42 41 40 39 38 37 36
44-Pin TQFP
C32
C42
C52
CD11
CD21
C31
CS
DIO
FS
TSCA
DXA
Am79Q021VC PCLK
VOUT1
VIN2
VOUT2
VCCA
AGND
VIN1
VREF
VOUT3
VIN3
C41
DCLK
DGND
43CD22
44CD12
35C51 34MCLK/E1
12 13 14 15 16 17 18 19 20 CD13
21 22
CD23
C33
C43
C53
CD14
CD24
C34
C44
C54
DRA
24 RST
23 INT
10
VOUT4 11
VIN4
19256A-023
Am79Q02/021/031
Quad Subscriber Line Audio-Processing Circuit
(QSLAC™) Devices
DISTINCTIVE CHARACTERISTICS
Performs the functions of four codec/filters
Software programmable:
— SLIC input impedance
— Transhybrid balance
— Transmit and receive gains
— Equalization (frequency response)
— Digital I/O pins
— Programmable debouncing on one input
— Time slot assigner
— Programmable clock slot and PCM transmit clock
edge options
Standard microprocessor interface
A-law, μ-law, or linear coding
Single or Dual PCM ports available
— Up to 128 channels (PCLK at 8.192 MHz) per
PCM port
— Optional supervision on the PCM highway
1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144,
6.176, or 8.192 MHz master clock derived from
MCLK or PCLK
Built-in test modes with loopback, tone
generation, and μP access to PCM data
Low-power, 5.0 V CMOS technology
5.0 V only operation
Mixed state (analog and digital) impedance
scaling
Performance characteristics guaranteed over a
12 dB gain range
Real Time Data register with interrupt (open
drain or TTL output)
Supports multiplexed SLIC inputs
Broadcast state
256 kHz or 293 kHz chopper clock for Legerity
SLICs with switching regulator
Maximum channel bandwidth for V.34 modems
